- 30 12月, 2012 4 次提交
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由 Dave Airlie 提交于
This reverts commit 83c0bcb6. Lucas pointed out this was a mistake, and I missed the discussion, so just revert it out to save a rebase. Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Lucas Stach 提交于
The intention is to program exactly WIN_A, not WIN_A and possibly others. Signed-off-by: NLucas Stach <dev@lynxeye.de> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Lucas Stach 提交于
Window properties are programmed through a shared aperture and have to happen atomically. Also we do the read-update-write dance on some of the shared regs. To make sure that different functions don't stumble over each other protect the register access with a mutex. Signed-off-by: NLucas Stach <dev@lynxeye.de> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Lucas Stach 提交于
Fixes wrong picture offset observed when using HDMI output with a Technisat HD TV. Signed-off-by: NLucas Stach <dev@lynxeye.de> Acked-by: NMark Zhang <markz@nvidia.com> Tested-by: NMark Zhang <markz@nvidia.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 28 11月, 2012 2 次提交
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由 Thierry Reding 提交于
Add support for host1x, the display controllers and HDMI on the Tegra30 SoC. Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Tested-by: NStephen Warren <swarren@nvidia.com> Tested-by: NMark Zhang <markz@nvidia.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Thierry Reding 提交于
Instead of using the stride derived from the display mode, use the pitch associated with the currently active framebuffer. This fixes a bug where the LCD display content would be skewed when enabling HDMI with a video mode different from that of the LCD. Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Tested-by: NTerje Bergstrom <tbergstrom@nvidia.com> Tested-by: NMark Zhang <markz@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 20 11月, 2012 1 次提交
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由 Thierry Reding 提交于
This commit adds a KMS driver for the Tegra20 SoC. This includes basic support for host1x and the two display controllers found on the Tegra20 SoC. Each display controller can drive a separate RGB/LVDS output. Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NMark Zhang <markz@nvidia.com> Reviewed-by: NMark Zhang <markz@nvidia.com> Tested-by: NMark Zhang <markz@nvidia.com> Tested-and-acked-by: NAlexandre Courbot <acourbot@nvidia.com> Acked-by: NTerje Bergstrom <tbergstrom@nvidia.com> Tested-by: NTerje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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