The Rockchip support is not limited to Cortex-A9 socs anymore and its
presence may confuse people reading /proc/cpuinfo. So remove the core
specific part.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>

It's a basic version of suspend and resume for rockchip,
it only support RK3288 now.
Signed-off-by: NTony Xie <xxx@rock-chips.com>
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Tested-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch add basic rk3288 smp support.

Only cortex-A9 need invalid L1, A7/A12/A15/A17 should not invalid L1, since
for A7/A12/A15, the invalidation would be taken as clean and invalidate.

If you use the software manual invalidation instead of hardware invalidation
(assert l1/l2rstdisable during reset) after reset, there is tiny change that
some cachelines would be in dirty and valid state after reset(since the ram
content would be random value after reset), then the unexpected clean might
lead to system crash.

It is a known issue for the A12/A17 MPCore multiprocessor that the active
processors might be stalled when the individual processor is powered down,
we can avoid this prolbem by softreset the processor before power it down.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Makes it possible to define a rockchip,pmu phandle in the cpus node directly
referencing the pmu syscon instead of searching for specific compatible.

The old way of finding the pmu stays of course available.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The pmu register space is - like the GRF - shared by quite some peripherals.
On the rk3188 and rk3288 even parts of the pinctrl are living there.
Therefore we normally shouldn't map it a second time when the syscon
does this already.

Therefore convert the cpu power-domain handling to access the pmu via a
regmap and at first try to get it via the syscon interface.
Getting this syscon will only fail if the pmu node does not have the
"syscon" compatible and thus does not get shared with other drivers.

In this case we map it like before and create the necessary regmap on
top of it.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

cpufreq-cpu0 got renamed to a more generic name cpufreq-dt, so
adapt the created platform-device to this.
Reported-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Rockchip SoCs can sucessfully use the generic cpufreq-cpu0 driver to
do frequency scaling. Therefore add a platform device in the machine
init code.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This is needed to access the pl330 dma controllers on Rockchip SoCs.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NKever Yang <kever.yang@rock-chips.com>

Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NWill Deacon <will.deacon@arm.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Adds ability to shutdown all CPUs except the first one
(since it might be special for a lot of platforms).
It is now possible to use kexec which requires such a feature.
Signed-off-by: NRomain Perier <romain.perier@gmail.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

When compiling for multiplatform for both ARMv6 and ARMv7, the default
compiler flags are for ARMv6, and the following cpu-hotplug change will
fail with:
 /tmp/ccSFxfmI.s:68: Error: selected processor does not support ARM mode `isb '
 /tmp/ccSFxfmI.s:74: Error: selected processor does not support ARM mode `isb '
 /tmp/ccSFxfmI.s:75: Error: selected processor does not support ARM mode `dsb '

Fix this in a similar manner as in commit 9f0affcf "ARM: mvebu: Fix pmsu
compilation when ARMv6 is selected", by specifying ARMv7 flags for platsmp.o.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

All known Rockchip SoCs have a reset controller in their CRUs, so it's
helpful to have the reset controller framework selected by default,
only be deselected by the user in special cases.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-By: NMax Schwarz <max.schwarz@online.de>
Tested-By: NMax Schwarz <max.schwarz@online.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.  This also allows us to eliminate the
.init_machine function as this becomes the same as the generic version.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

With the newly introduced CPU_METHOD_OF_DECLARE is not necessary anymore
to reference the relevant smp_ops in the board file, but instead it can
simply be set by the enable-method property of the cpu nodes.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

They're u32, they're not unsigned long.  The UL suffix is not required
here.
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The error emitted when mapping the pmu failed, wrongly mentions the sram.
Reported-by: NKent Borg <kentborg@borg.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This adds the necessary smp-operations and startup code to use
additional cores on Rockchip SoCs.

We currently hog the power management unit in the smp code, as it is
necessary to control the power to the cpu core and nothing else is
currently using it, so a generic implementation can be done later.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NUlrich Prinz <ulrich.prinz@googlemail.com>

This adds the device-node and config select to enable the
scu in all Rockchip Cortex-A9 SoCs.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NUlrich Prinz <ulrich.prinz@googlemail.com>

All V7 platforms can run SMP kernels, so make CONFIG_SMP visible for V7
multi-platform builds.
Signed-off-by: NRob Herring <robh@kernel.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Multi-platform requires various kconfig options to be selected, so
platforms don't need to select them individually.
Signed-off-by: NRob Herring <robh@kernel.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: NStephen Warren <swarren@nvidia.com>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

RK2928 and RK3066 contain a dw_apb timer component, while the rk3188 uses
a slightly similar but still different timer component. But all of them
support the ARM-global-timer that got added as clocksource driver recently.

So enable support for it to get a working clocksource for rk3188.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

CONFIG_LOCAL_TIMERS was removed in february, so the twd never gets
selected. Fix this by making the twd depend on SMP directly.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

With arch/arm calling of_clk_init(NULL) from time_init(), we can now
remove custom .init_time hooks.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>

This adds a generic devicetree board file and a dtsi for boards
based on the RK3066a SoCs from Rockchip.

Apart from the generic parts (gic, clocks, pinctrl) the only components
currently supported are the timers, uarts and mmc ports (all DesignWare-
based).
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NOlof Johansson <olof@lixom.net>