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  1. 13 6月, 2013 1 次提交
  3. 11 6月, 2013 1 次提交
  5. 18 5月, 2013 1 次提交
  7. 01 5月, 2013 1 次提交
  9. 30 4月, 2013 1 次提交
  11. 20 4月, 2013 2 次提交
  13. 01 4月, 2013 3 次提交
    • S
      sh_eth: make 'link' field of 'struct sh_eth_private' *int* · 3340d2aa
      由 Sergei Shtylyov 提交于 
      The 'link' field of 'struct sh_eth_private' has type 'enum phy_state' while the
'link' field of 'struct phy_device' is merely *int* (having values 0 and 1) and
the former field gets assigned from the latter. Make the field match, getting
rid of incorrectly used PHY_DOWN value in assignments/comparisons.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3340d2aa
    • S
      sh_eth: workaround for spurious ECI interrupt · 3893b273
      由 Sergei Shtylyov 提交于 
      At least on Renesas R8A7778, EESR.ECI interrupt seems to fire regardless of its
mask in EESIPR register. I can 100% reproduce it with the following scenario:
target is booted with 'ip=on' option, and so IP-Config opens SoC Ether device
but doesn't get a proper reply and then succeeds with on-board SMC chip; then
I login and try to bring up the SoC Ether device with 'ifconfig', and I get
an ECI interrupt once request_irq() is called by sh_eth_open() (while interrupt
mask in EESIPR register is all 0), if that interrupt is accompanied by a pending
EESR.FRC (frame receive completion) interrupt, I get kernel oops in sh_eth_rx()
because sh_eth_ring_init() hasn't been called yet!

The solution I worked out is the following: in sh_eth_interrupt(), mask the
interrupt status from EESR register with the interrupt mask from EESIPR register
in order not to handle the disabled interrupts -- but forcing EESIPR.M_ECI bit
in this mask set because we always need to fully handle EESR.ECI interrupt in
sh_eth_error() in order to quench it (as it doesn't get cleared by just writing
1 to the this bit as all the other interrupts).

While at it, remove unneeded initializer for 'intr_status' variable and give it
*unsigned long* type, matching the type of sh_eth_read()'s result; fix comment.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: NMax Filippov <max.filippov@cogentembedded.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3893b273
    • S
      sh_eth: fix handling of no LINK signal · 1e1b812b
      由 Sergei Shtylyov 提交于 
      The code handling the absent LINK signal (or the absent PSR register -- which
reflects the state of this signal) is quite naive and has probably never really
worked.  It's probably enough to say that this code is executed only on the LINK
change interrupt (sic!) but even if we actually have the signal and choose to
ignore it (it might be connected to PHY's link/activity LED output as on the
Renesas BOCK-W board), sh_eth_adjust_link() on which this code relies to update
'mdp->link' gets executed later than the LINK change interrupt where it is
checked, and so RX/TX never get enabled via ECMR register.

So, ignore the LINK changed interrupt iff LINK signal is absent (or just chosen
not to be used) or PSR register is absent, and enable/disable RX/TX directly in
sh_eth_adjust_link() in this case.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1e1b812b
  15. 30 3月, 2013 2 次提交
    • S
      sh_eth: add R-Car support for real · a3f109bd
      由 Sergei Shtylyov 提交于 
      Commit d0418bb7 (net: sh_eth: Add eth support
for R8A7779 device) was a failed attempt to add support for one of members of
the R-Car SoC family.  That's for three reasons: it treated R8A7779 the  same
as SH7724 except including quite dirty hack adding ECMR_ELB  bit  to the mask
in sh_eth_set_rate() while not removing ECMR_RTM bit (despite it's reserved in
R-Car Ether), and it didn't add a new register offset array despite the closest
SH_ETH_REG_FAST_SH4 mapping differs by 0x200 to the offsets all the R-Car Ether
registers have, and also some of the registers in this old mapping don't exist
on R-Car Ether (due to this, SH7724's 'sh_eth_my_cpu_data' structure is not
adequeate for R-Car too).  Fix all these shortcomings, restoring the SH7724
related section to its pristine state...
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a3f109bd
    • S
      sh_eth: move data from header file to driver · c0013f6f
      由 Sergei Shtylyov 提交于 
      The driver's header file contains initialized register offset tables which (as
any data definitions), of course, have no business being there.  Move them  to
the driver's body, somewhat beautifying the initializers, while at it...
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c0013f6f
  17. 22 3月, 2013 4 次提交
  19. 21 3月, 2013 3 次提交
  21. 15 3月, 2013 1 次提交
  23. 05 2月, 2013 1 次提交
  25. 15 1月, 2013 1 次提交
  27. 04 11月, 2012 1 次提交
  29. 08 10月, 2012 1 次提交
    • P
      drivers/net/ethernet/renesas/sh_eth.c: fix error return code · 043c4789
      由 Peter Senna Tschudin 提交于 
      The function sh_eth_drv_probe() return 0 for success and negative value
for most of its internal tests failures. There is one exception
that is error case going to out_release:. For this error case, the
function abort its success execution path, but returns non negative
value, making it difficult for a caller function to notice the error.

This patch fixes the error case that do not return negative value.

This was found by Coccinelle, but the code change was made by hand.
This patch is not robot generated.

A simplified version of the semantic match that finds this problem is
as follows: (http://coccinelle.lip6.fr/)

// <smpl>
(
if@p1 (\(ret < 0\|ret != 0\))
 { ... return ret; }
|
ret@p1 = 0
)
... when != ret = e1
    when != &ret
*if(...)
{
  ... when != ret = e2
      when forall
 return ret;
}
// </smpl>
Signed-off-by: NPeter Senna Tschudin <peter.senna@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      043c4789
  31. 20 8月, 2012 1 次提交
  33. 27 6月, 2012 4 次提交
  35. 26 6月, 2012 2 次提交
  37. 23 6月, 2012 1 次提交
  39. 30 5月, 2012 1 次提交
  41. 05 4月, 2012 1 次提交
  43. 02 4月, 2012 1 次提交
  45. 28 3月, 2012 1 次提交
  47. 17 2月, 2012 4 次提交