- 10 4月, 2015 2 次提交
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由 Daniel Vetter 提交于
It's not needed since the worker rechecks that it didn't race. We only need to cancel synchronously after disabling drrs to make sure the worker really is gone (e.g. for driver unload). But for normal operation the stall is just wasted time. Reported-by: NChris Wilson <chris@chris-wilson.co.uk> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ramalingam C <ramalingam.c@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Vandana Kannan <vandana.kannan@intel.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com> Signed-off-by: NJani Nikula <jani.nikula@intel.com>
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由 Daniel Vetter 提交于
We must acquire the mutex before we can check drrs.dp, otherwise someone might sneak in with a modeset, clear the pointer after we've checked it and then the code will Oops. This issue has been introduced in commit a93fad0f Author: Vandana Kannan <vandana.kannan@intel.com> Date: Sat Jan 10 02:25:59 2015 +0530 drm/i915: DRRS calls based on frontbuffer v2: Don't blow up on uninitialized mutex and work item by checking whether DRRS is support or not first. Also unconditionally initialize the mutex/work item to avoid future trouble. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ramalingam C <ramalingam.c@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Vandana Kannan <vandana.kannan@intel.com> Cc: stable@vger.kernel.org (4.0+ only) Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Tested-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com> Signed-off-by: NJani Nikula <jani.nikula@intel.com>
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- 27 3月, 2015 2 次提交
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The function intel_dp_set_drrs_state() would decide which pipe to downclock based on the staged config for the given connector. However, the result of that function is immediate, and it uses input values from crtc->config, so it should be looking at the current crtc instead. Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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Move towards atomic by using the legacy modeset's drm_atomic_state instead. Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 26 3月, 2015 1 次提交
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So that we can add connector states to the drm_atomic_state used in the legacy modeset. Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 24 3月, 2015 1 次提交
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由 Ramalingam C 提交于
As part of allocation of the drm_i915_private variable, drrs capability enum is initialized to DRRS_NOT_SUPPORTED. Hence need not initialize at each connector init. Moreover initializing this enum at connector init will reset the successful DRRS initialization of previous connector, as we have the DRRS support for only one panel at a time. Signed-off-by: NRamalingam C <ramalingam.c@intel.com> Reviewed-by: NSivakumar Thulasimani <sivakumar.thulasimani@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 20 3月, 2015 16 次提交
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由 Ville Syrjälä 提交于
AUX addresses are 20 bits long. Send out the entire address instead of just the low 16 bits. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NJani Nikula <jani.nikula@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Jani Nikula 提交于
Allow for a larger receive data size, and check if the receiver returned the number of bytes written. Without this, we've basically skipped all the unwritten bytes for short writes. Signed-off-by: NJani Nikula <jani.nikula@intel.com> Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
To keep things clear rename the intel_dp->supported_rates[] to intel_dp->sink_rates[], and rename the supported_rates[] name we used elsewhere for the intersection of source and sink rates to common_rates[]. Cc: Sonika Jindal <sonika.jindal@intel.com> Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NSonika Jindal <sonika.jindal@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
TODO: Is there an actually nice way to print an array of ints? Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NSonika Jindal <sonika.jindal@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
"P1273_DPLL_Programming Spreadsheet.xlsm" lists a boatload of frequencies for eDP. Try to use them all. For now I've decided not to add hardcoded DPLL dividers for these cases since chv_find_best_dpll() works just fine. I've not actually tested any of these since I don't have an eDP 1.4 panel. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NSonika Jindal <sonika.jindal@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
Complain loudly if we ever attempt to overflow the the supported_rates[] array. This should never happen since the sink_rates[] array will always be smaller or of equal size. But should someone change that we want to catch it without scribblign over the stack. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NSonika Jindal <sonika.jindal@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
Now that intel_dp_max_link_bw() no longer considers the source restrictions we may try to enable MST with 5.4GHz even when the source doesn't support it. To fix that switch the code over to handle the link rate in the same way as the SST code handles it. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NSonika Jindal <sonika.jindal@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
Drop the gen9 checks from the code and issue DP_LINK_RATE_SET whenever the sink reports to support it. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NSonika Jindal <sonika.jindal@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
Consider the link rates reported by the sink via DP_SUPPORTED_LINK_RATES when checking modes against the max link rate. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NSonika Jindal <sonika.jindal@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
intel_dp_compute_config() only really needs to know the rates supported by both source and sink, so hide the raw source and sink arrays from it. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NSonika Jindal <sonika.jindal@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
Remove the sink vs. source limit mess from intel_dp_max_link_bw() and just move the source restriction checks to intel_dp_source_rates(). Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NSonika Jindal <sonika.jindal@intel.com> [danvet: Resolve conflict with WaDisableHBR2:skl patch.] Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
Now that both source and sink rates are always filled in there's no need for any special cases in intel_supported_rates(). Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NSonika Jindal <sonika.jindal@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
Once we've read the rates from the sink we don't have to mess with them, so the caller can just look at the stored rates without doing extra copies. If the sink doesn't support the new link rate stuff, we just point the caller at the default_rates[] array. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NSonika Jindal <sonika.jindal@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
The source rates don't change, so we can just point the caller at the const arrays. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NSonika Jindal <sonika.jindal@intel.com> Reviewed-by: NTodd Previte <tprevite@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
No point in converting from hardware format every single time, just store the rates in the final format under intel_dp. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NSonika Jindal <sonika.jindal@intel.com> Reviewed-by: NTodd Previte <tprevite@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
No point in using uint32_t here, just plain old int will do. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NSonika Jindal <sonika.jindal@intel.com> Reviewed-by: NTodd Previte <tprevite@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 18 3月, 2015 5 次提交
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由 Damien Lespiau 提交于
v2: Use the recently introduced INTEL_REVID() and SKL_REVID defines (Nick Hoath) Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-by: NJesse Barnes <jbarnes@virtuousgeek.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89554Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Sonika Jindal 提交于
v2: Making the link_clock half in switch inline with the DPLL_CTRL1_* macros (Ville) Signed-off-by: NSonika Jindal <sonika.jindal@intel.com> Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Sonika Jindal 提交于
eDp 1.4 supports custom frequencies. Skylake supports following intermediate frequencies : 3.24 GHz, 2.16 GHz and 4.32 GHz along with usual LBR, HBR and HBR2 frequencies. Read sink supported frequencies and get common frequencies from sink and source and use these for link training. v2: Rebased, removed calculation of min_clock since for edp it is taken as max_clock (as per comment). v3: Keeping single array for link rates (Satheesh) v4: Setting LINK_BW_SET to 0 when setting LINK_RATE_SET (Satheesh) v5: Some minor nits (Ville) v6: Keeping separate arrays for source and sink rates (Ville) v7: Remove redundant setting of DP_LINK_BW_SET to 0 (Ville) Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NSonika Jindal <sonika.jindal@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Sonika Jindal 提交于
v2: Using DP_SUPPORTED_LINK_RATES macro for supported_rates array (Satheesh). v3: Reading dpcd's supported link rates tables based upon edp version in the same patch. v4: Move version check under is_edp (Satheesh) v5: Using le16 for rates, some naming, and removing nested if block (Ville) v6: Correctly using DP_MAX_SUPPORTED_RATES and removing DP_SUPPORTED_LINK_RATES (Ville) v7: Incorrectly removed DP_SUPPORTED_LINK_RATES in v6, re-adding it v8: Checking return value of intel_dp_dpcd_read_wake() (Ville) Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NSonika Jindal <sonika.jindal@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ramalingam C 提交于
In invalidate and flush functions of eDP DRRS, if deferred downclock work starts execution at a time window between acquiring the drrs mutex and cancellation of the deferred work (intel_edp_drrs_downclock_work), then deferred work will find drrs mutex locked and wait for the same. Meanwhile the function that acquired mutex drrs invalidate/flush will wait for the completion of the deferred work before releasing the mutex. Thats a deadlock. To avoid such deadlock scenario, this change cancels the deferred work before acquiring the mutex at invalidate and flush functions. Signed-off-by: NRamalingam C <ramalingam.c@intel.com> Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 25 2月, 2015 1 次提交
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由 Sonika Jindal 提交于
Based upon vbt's vswing preemph settings value select the appropriate translations for edp. v2: Incorporating bspec changes for vswing and preemph levels, adding edp translation table. Removed HSW from selection 9 which is specific to skl and correcting the returning of level2 from max pre emph (Damien) v3: Rebasing on top of renaming patches. Adding level(3,0) since level(2,2) as mentioned in bspec is invalid as per edp spec. Also changed the determining of size of the table selected (Satheesh). v4: Adding level 3 in max voltage selection if low vswing is selected (Satheesh) v5: Add a comment stating that skl_ddi_translations_edp is for eDP 1.4 low vswing panels. v6: Updating recommended DDI translation table for edp 1.4 Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v4) Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> (v6) Signed-off-by: NSonika Jindal <sonika.jindal@intel.com> Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 24 2月, 2015 5 次提交
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由 Ramalingam C 提交于
When Downclock mode is not found, the same info is added to the corresponding debug log. Signed-off-by: NRamalingam C <ramalingam.c@intel.com> Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Vandana Kannan 提交于
Adding an overview of DRRS in general and the implementation for eDP DRRS. Also, describing the functions related to eDP DRRS. Signed-off-by: NVandana Kannan <vandana.kannan@intel.com> Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Durgadoss R 提交于
This patch enables eDP DRRS for CHV by adding the required IS_CHERRYVIEW() checks. CHV uses the same register bit as VLV. [Vandana]: Since CHV has 2 sets of M_N registers, it will follow the same code path as gen < 8. Added CHV check in dp_set_m_n() [Ram]: Rebased on top of previous patch modifications Signed-off-by: NDurgadoss R <durgadoss.r@intel.com> Signed-off-by: NVandana Kannan <vandana.kannan@intel.com> Signed-off-by: NRamalingam C <ramalingam.c@intel.com> Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Vandana Kannan 提交于
Definition of VLV RR switch bit and corresponding toggling in set_drrs function. Signed-off-by: NVandana Kannan <vandana.kannan@intel.com> Signed-off-by: NUma Shankar <uma.shankar@intel.com> Reviewed-by: NJani Nikula <jani.nikula@intel.com> Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Vandana Kannan 提交于
For Broadwell, there is one instance of Transcoder MN values per transcoder. For dynamic switching between multiple refreshr rates, M/N values may be reprogrammed on the fly. Link N programming triggers update of all data and link M & N registers and the new M/N values will be used in the next frame that is output. V2: [By Ram]: intel_dp_set_m_n() is rewritten to accommodate gen >= 8 [Rodrigo] V3: Coding style correction [Ram] V4: [By Ram] intel_dp_set_m_n modifications are moved into a separate patch, retaining only DRRS related changes here [Rodrigo] Signed-off-by: NVandana Kannan <vandana.kannan@intel.com> Signed-off-by: NPradeep Bhat <pradeep.bhat@intel.com> Signed-off-by: NRamalingam C <ramalingam.c@intel.com> Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 14 2月, 2015 2 次提交
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由 Damien Lespiau 提交于
This was introduced in: commit 0bc12bcb Author: Rodrigo Vivi <rodrigo.vivi@intel.com> Date: Fri Nov 14 08:52:28 2014 -0800 drm/i915: Introduce intel_psr.c But the unpack function is unused at this date. Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Damien Lespiau 提交于
This function is only used in intel_dp.c since: commit 0e32b39c Author: Dave Airlie <airlied@redhat.com> Date: Fri May 2 14:02:48 2014 +1000 drm/i915: add DP 1.2 MST support (v0.7) Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 11 2月, 2015 1 次提交
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由 Ville Syrjälä 提交于
Return IRQ_HANDLED from intel_dp_hpd_pulse() to properly ignore the long HPD pulse on eDP to avoid the never ending VDD off->HPD->VDD on->VDD off->HPD... cycle. This fixes a regression intoduced by commit b2c5c181 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Fri Jan 23 06:00:31 2015 +0100 drm/i915: Use symbolic irqreturn for ->hpd_pulse Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jani Nikula <jani.nikula@linux.intel.com> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NJani Nikula <jani.nikula@intel.com>
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- 10 2月, 2015 1 次提交
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由 Daniel Vetter 提交于
Nothing in Bspec seems to indicate that we actually needs this, and it looks like can't work since by this point the pipe is off and so vblanks won't really happen any more. Note that Bspec mentions that it takes a vblank for this bit to change, but _only_ when enabling. Dropping this code quenches an annoying backtrace introduced by the more anal checking since commit 51e31d49 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Mon Sep 15 12:36:02 2014 +0200 drm/i915: Use generic vblank wait Note: This fixes the fallout from the above commit, but does not address the shortcomings of the IBX transcoder select workaround implementation discussed during review [1]. [1] http://mid.gmane.org/87y4o7usxf.fsf@intel.com Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86095Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com> Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Cc: stable@vger.kernel.org # 3.19 Signed-off-by: NJani Nikula <jani.nikula@intel.com>
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- 27 1月, 2015 3 次提交
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由 Matt Roper 提交于
Even though we only support atomic plane updates at the moment, we still need to add an .atomic_get_property() entrypoint for connectors before we allow the driver to flip on the DRIVER_ATOMIC bit. As soon as that bit gets set, the DRM core will start adding atomic connector properties (in addition to the plane properties we care about at the moment), so we need to be able to handle the new way the DRM core will interact with us. For simplicity, we just lookup driver-specific connector properties in the usual shadow array maintained by the core. Once we get real atomic modeset support for crtc's and planes, this code should be re-written to pull the data out of crtc/connector state structures. v2: Fix intel_dvo and intel_dsi that I missed on the first pass (Ander) Signed-off-by: NMatt Roper <matthew.d.roper@intel.com> Reviewed-by: NAnder Conselvan de Oliveira <conselvan2@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Matt Roper 提交于
We want to enable/test plane updates via the atomic interface, but as soon as we flip DRIVER_ATOMIC on, the DRM core will take some atomic codepaths to lookup properties during drmModeGetConnector() and some of those codepaths unconditionally dereference connector->state (specifically when looking up the CRTC ID property in drm_atomic_connector_get_property()). Create a dummy connector state for each connector at init time to ensure the DRM core doesn't try to dereference a NULL connector->state. The actual connector properties will never be updated or contain useful information, but since we're doing this specifically for testing/debug of the plane operations (and only when a specific kernel module option is given), that shouldn't really matter. Once we start creating connector states, the DRM core will want to be able to clean them up for us. We also need to hook up the destruction entrypoint to the core's helper. v2: Squash in the patch to set the state destruction hook (Ander & Bob) v3: Only create dummy connector states when we're actually faking atomic support. (Ander) Signed-off-by: NMatt Roper <matthew.d.roper@intel.com> Reviewed-by: NAnder Conselvan de Oliveira <conselvan2@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Vandana Kannan 提交于
Calls have been added to invalidate/flush DRRS whenever invalidate/flush is called as part of frontbuffer tracking. Apart from calls as a result of GEM tracking to fb invalidate/flush, a call has been added to invalidate fb obj from crtc_page_flip as well. This is to track busyness through flip calls. The call to fb_obj_invalidate (in flip) is placed before queuing flip for this obj. drrs_invalidate() and drrs_flush() check for drrs.dp which would be NULL if it was setup in drrs_enable(). This covers for the condition when DRRS is not supported. v2: Removing the call to invalidate_drrs from page_flip. This has not been tested on Android yet, but, in case DRRS transtions do not work as expected, check by adding back this call in page_flip. Signed-off-by: NVandana Kannan <vandana.kannan@intel.com> Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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