1. 02 12月, 2011 1 次提交
  2. 03 10月, 2011 1 次提交
    • A
      OMAPDSS/OMAP_VOUT: Fix incorrect OMAP3-alpha compatibility setting · 11354dd5
      Archit Taneja 提交于
      On OMAP3, in order to enable alpha blending for LCD and TV managers, we needed
      to set LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits in DISPC_CONFIG. On
      OMAP4, alpha blending is always enabled by default, if the above bits are set,
      we switch to an OMAP3 compatibility mode where the zorder values in the pipeline
      attribute registers are ignored and a fixed priority is configured.
      
      Rename the manager_info member "alpha_enabled" to "partial_alpha_enabled" for
      more clarity. Introduce two dss_features FEAT_ALPHA_FIXED_ZORDER and
      FEAT_ALPHA_FREE_ZORDER which represent OMAP3-alpha compatibility mode and OMAP4
      alpha mode respectively. Introduce an overlay cap for ZORDER. The DSS2 user is
      expected to check for the ZORDER cap, if an overlay doesn't have this cap, the
      user is expected to set the parameter partial_alpha_enabled. If the overlay has
      ZORDER cap, the DSS2 user can assume that alpha blending is already enabled.
      
      Don't support OMAP3 compatibility mode for now. Trying to read/write to
      alpha_blending_enabled sysfs attribute issues a warning for OMAP4 and does not
      set the LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits.
      
      Change alpha_enabled to partial_alpha_enabled in the omap_vout driver. Use
      overlay cap "OMAP_DSS_OVL_CAP_GLOBAL_ALPHA" to check if overlay supports alpha
      blending or not. Replace this with checks for VIDEO1 pipeline.
      
      Cc: linux-media@vger.kernel.org
      Cc: Lajos Molnar <molnar@ti.com>
      Signed-off-by: NArchit Taneja <archit@ti.com>
      Acked-by: NVaibhav Hiremath <hvaibhav@ti.com>
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      11354dd5
  3. 30 9月, 2011 17 次提交
  4. 20 9月, 2011 1 次提交
  5. 01 8月, 2011 1 次提交
    • T
      HACK: OMAP: DSS2: clk hack for OMAP2/3 · 9ede365a
      Tomi Valkeinen 提交于
      The HWMOD data for OMAP2 and 3 are currently not up to date regarding
      DSS (OMAP4 HWMOD data is fine). This patch makes the DSS driver to get
      the opt clocks needed for OMAP2/3 with the old clock names, thus
      allowing DSS driver to use runtime PM.
      
      The HWMOD databases should be fixes ASAP, and this patch can be reverted
      after that.
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      9ede365a
  6. 25 7月, 2011 2 次提交
  7. 01 7月, 2011 2 次提交
    • T
      OMAP: DSS2: Fix FIFO threshold and burst size for OMAP4 · 5ed8cf5b
      Tomi Valkeinen 提交于
      The DMA FIFO threshold registers and burst size registers have changed
      for OMAP4.  The current code only handles OMAP2/3 case, and so the
      values are a bit off for OMAP4.  A summary of the differences between
      OMAP2/3 and OMAP4:
      
      Burst size:
      OMAP2/3: 4 x 32 bits / 8 x 32 bits / 16 x 32 bits
      OMAP4: 2 x 128 bits / 4 x 128 bits / 8 x 128 bits
      
      Threshold size:
      OMAP2/3: in bytes (8 bit units)
      OMAP4: in 128bit units
      
      This patch fixes the issue by creating two new helper functions in
      dss_features: dss_feat_get_buffer_size_unit() and
      dss_feat_get_burst_size_unit(). These return (in bytes) the unit size
      for threshold registers and unit size for burst size register,
      respectively, and are used to calculate correct values.
      
      For the threshold size the usage is straightforward. However, the burst
      size register has different multipliers for OMAP2/3 and OMAP4. This
      patch solves the problem by defining the multipliers for the burst size
      as 2x, 4x and 8x, which fit fine for the OMAP4 burst size definition
      (i.e. burst size unit for OMAP4 is 128bits), but requires a slight twist
      on OMAP2/3 by defining the burst size unit as 64bit.
      
      As the driver in practice always uses the maximum burst size, and no use
      case currently exists where we would want to use a smaller burst size,
      this patch changes the driver to hardcode the burst size when
      initializing DISPC. This makes the threshold configuration code somewhat
      simpler.
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      5ed8cf5b
    • T
      OMAP: DSS2: Add Color Phase Rotation support · 3c07cae2
      Tomi Valkeinen 提交于
      Add Color Phase Rotation (CPR) support and sysfs files to enable CPR and
      to set the CPR coefficient matrix.
      
      CPR is enabled via manager?/cpr_enable file, and the coefficient matrix
      is set via manager?/cpr_coef file. The values in cpr_coef are in the
      following order:
      
      RR RG RB GR GG GB BR BG BB
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      3c07cae2
  8. 23 5月, 2011 1 次提交
    • A
      OMAP: DSS2: Add support for NV12 format · 0d66cbb5
      Amber Jain 提交于
      Add the support for NV12 color format.
      Configure base address for UV component of NV12 color format.
      Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling
      chroma-resampling for video pipeline and hence using FIR2 register set for
      scaling UV.
      Changes to _dispc_set_scaling(), because of the reason above, are:
      - call _dispc_set_scaling_common() to handle scaling for all color formats
        except for OMAP4 where it only handles scaling for RGB or Y-component
      - call _dispc_set_scaling_uv() for special handling required for UV
        component on OMAP4.
      - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes.
      
      Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by
      Lajos Molnar <molnar@ti.com>
      Signed-off-by: NAmber Jain <amber@ti.com>
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      0d66cbb5
  9. 13 5月, 2011 5 次提交
  10. 11 5月, 2011 2 次提交
    • T
      OMAP: DSS2: DSI: add option to leave DSI lanes powered on · 2a89dc15
      Tomi Valkeinen 提交于
      The DSI pins are powered by VDDS_DSI. If VDDS_DSI is off, the DSI pins
      are floating even if they are pinmuxed to, say, safe mode and there's a
      pull down/up.
      
      This patch gives the panel drivers an option to leave the VDDS_DSI power
      enabled while the DSS itself is turned off. This can be used to keep the
      DSI lanes in a valid state while DSS is off, if the DSI pins are muxed
      for pull down (not done in this patch).
      
      There will be a slight power consumption increase (~100 uA?) when the
      VDDS_DSI is left on, but because this option is used when the panel is
      left on, the regulator consumption is negligible compared to panel power
      consumption.
      
      When the panel is fully turned off the VDDS_DSI is also turned off.
      
      As an added bonus this will give us faster start up time when starting
      up the DSS and the regulator is already enabled.
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      2a89dc15
    • A
      OMAP2PLUS: DSS2: Change enum "dss_clk_source" to "omap_dss_clk_source" · 89a35e51
      Archit Taneja 提交于
      Change enum dss_clk_source to omap_dss_clock_source and move it to
      'plat/display.h'. Change the enum members to attach "OMAP_" in the beginning.
      These changes are done in order to specify the clock sources for DSS in the
      board file.
      Signed-off-by: NArchit Taneja <archit@ti.com>
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      89a35e51
  11. 16 3月, 2011 4 次提交
  12. 15 3月, 2011 1 次提交
  13. 11 3月, 2011 2 次提交
    • T
      OMAP4: DSS2: Clock source changes for OMAP4 · ea75159e
      Taneja, Archit 提交于
      On OMAP3, the pixel clock for the LCD manager was derived through DISPC_FCLK as:
      
      Lcd Pixel clock = DISPC_FCLK / lcd / pcd
      
      Where lcd and pcd are divisors in the DISPC_DIVISOR register.
      
      On OMAP4, the pixel clocks for LCD1 and LCD2 managers are derived from 2 new
      clocks named LCD1_CLK and LCD2_CLK. The pixel clocks are calculated as:
      
      Lcd_o Pixel clock = LCDo_CLK / lcdo /pcdo, o = 1, 2
      
      Where lcdo and pcdo registers are divisors in DISPC_DIVISORo registers.
      
      LCD1_CLK and LCD2_CLK can have DSS_FCLK, and the M4 divider clocks of DSI1 PLL
      and DSI2 PLL as clock sources respectively. Introduce functions to select and
      get the clock source for these new clocks. Modify DISPC functions get the
      correct lck and pck rates based on the clock source of these clocks. Since
      OMAP2/3 don't have these clocks, force OMAP2/3 to always have the LCD_CLK source
      as DSS_CLK_SRC_FCK by introducing a dss feature.
      
      Introduce clock source names for OMAP4 and some register field changes in
      DSS_CTRL on OMAP4.
      
      Currently, LCD2_CLK can only have DSS_FCLK as its clock source as DSI2 PLL
      functionality hasn't been introduced yet. BUG for now if DSI2 PLL is selected as
      clock.
      Signed-off-by: NArchit Taneja <archit@ti.com>
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      ea75159e
    • T
      OMAP2PLUS: DSS2: Cleanup clock source related code · 66534e8e
      Taneja, Archit 提交于
      Clean up some of the DSS functions which select/get clock sources, use switch
      to select the clock source members since more clock sources will be introduced
      later on.
      
      Remove the use of macro CONFIG_OMAP2_DSS_DSI in dispc_fclk_rate, use a dummy
      inline for function for dsi_get_pll_hsdiv_dispc_rate() instead for code clarity.
      Signed-off-by: NArchit Taneja <archit@ti.com>
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      66534e8e