Move the Netlogic XLP device-trees to arch/mips/boot/dts/ and update the
Makefiles accordingly.  A built-in device-tree is optional, so select
BUILTIN_DTB when it is requested.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: David Daney <david.daney@cavium.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: Jayachandran C <jchandra@broadcom.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7560/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The XLP9XX SoC has an on-chip SATA controller with two ports. Add
ahci-init-xlp2.c to initialize the controller, setup the glue logic
registers, fixup PCI quirks and setup interrupt ack logic.
Signed-off-by: NGanesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6913/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

XLP3XX includes an on-chip SATA controller with 4 ports. The
controller needs glue logic initialization and PCI fixup before
it can be used with the standard AHCI driver.
Signed-off-by: NGanesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6872/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add support for the XLP5XX processor which is an 8 core variant of the
XLP9XX. Add XLP5XX cases to code which earlier handled XLP9XX.
Signed-off-by: NYonghong Song <ysong@broadcom.com>
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6871/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Calculate XLP 9XX and 2XX core frequency from the per-core PLL. This
should give the correct value for all board configurations.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6870/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Update PIC frequency calculation for XLP9XX and 2XX processors using
the correct PLL registers. This should work for all possible board
configurations.
Signed-off-by: NGanesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6876/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add the compatible property to the PIC entry. Also fix up the nodename
to use the correct address.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6869/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Use PRID_IMP_MASK macro instead of 0xff00 to extract the processor
type.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6868/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add IRQ to IRT (PIC interupt table index) mapping for SATA, GPIO, NAND
and SPI interfaces on the XLP SoC. Fix offsets for few blocks and add
device IDs for a few blocks.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6911/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The ELPA bit needs to be set in the PAGEGRAIN register to enable
access to >64GB physical address. Update reset.S to do this from
every hardware thread.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6866/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Update thread wakeup function to use scratch registers for saving SP and
RA. Move the register restore code needed for thread 0 to the calling
function. This reduces the size of code copied to the reset vector.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6910/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Use standard function to print cpumask. Also fixup a typo in the same
file.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: g@linux-mips.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6909/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Warn and return if invalid IRQ is passed to nlm_set_pic_extra_ack.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6862/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This is needed for nlm_node_present(0) to work on uniprocessor compile.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6861/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Nothing was using the method and there isn't any need for this hook.  This
leaves smp_cpus_done() empty for the moment.

As suggested by Paul Bolle <pebolle@tiscali.nl>.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Unify the various architectures __dtb_start and __dtb_end definitions
moving them into of_fdt.h.
Signed-off-by: NRob Herring <robh@kernel.org>
Acked-by: NVineet Gupta <vgupta@synopsys.com>
Acked-by: NJames Hogan <james.hogan@imgtec.com>
Tested-by: NMichal Simek <michal.simek@xilinx.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Jonas Bonn <jonas@southpole.se>
Cc: Chris Zankel <chris@zankel.net>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: linux-metag@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux@lists.openrisc.net
Cc: linux-xtensa@linux-xtensa.org
Tested-by: NGrant Likely <grant.likely@linaro.org>
Tested-by: NStephen Chivers <schivers@csc.com>

The existing code is buggy because built-in DTBs are in init memory.
It is also broken because the reserved bootmem was then freed after
unflattening, but the unflattened tree points to data in the flat tree.
Fix this by using the unflatten_and_copy_device_tree function.

This removes all accesses to FDT header data by the arch code.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Tested-by: NGrant Likely <grant.likely@linaro.org>

None of these files are actually using any __init type directives
and hence don't need to include <linux/init.h>.  Most are just a
left over from __devinit and __cpuinit removal, or simply due to
code getting copied from one driver to the next.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6320/

Move wakeup to after early console. This will allow us to display error
messages when cores are not woken up.  Also reduce the wait time for core
to come up.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6303/

The early serial code is not needed because we already have early
printk support provided by common/earlycons.c

This change also fixes the following build error that occurs when
CONFIG_SERIAL_8250 is not configured for Netlogic XLR boards:

arch/mips/built-in.o: In function `nlm_early_serial_setup':
setup.c:(.init.text+0x274): undefined reference to `early_serial_setup'
make: *** [vmlinux] Error 1
Reported-by: NMarkos Chandras <markos.chandras@imgtec.com>
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6083/

Add a default device tree fie for XLP9XX boards, and add code to use
this device tree if no DTB is passed to the kernel.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6287/

Support for adding legacy IRQ domain for XLP9XX. The node id of the
PIC has to be calulated differently for XLP9XX.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6286/

XLP9XX has a USB 3.0 controller on-chip with 2 xHCI ports. The USB
block is similar to the one on XLP2XX, so update usb-init-xlp2.c
to handle XLP9XX as well.
Signed-off-by: NGanesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6285/

Add PCI support for Netlogic XLP9XX. The PCI registers and
SoC bus numbers have changed in XLP9XX.

Also skip a few (bus,dev,fn) combinations which have issues when
read.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6284/

XLP9XX has 20 cores per node, opposed to 8 on earlier XLP8XX.
Update code that calculates node id from cpu id to handle this.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6283/

Update bridge code. Add code to the XLP9XX registers for DRAM
size, limit and node when running on XLPXX
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6282/

Update IO offset of the early console UART.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6281/

Add the SYS block registers for XLP9XX, most of them have changed.
The wakeup sequence has been updated to set the coherent mode from
the main thread rather than the woken up thread.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6280/

Functions for the XLP9XX interrupt table entry format and other PIC
register changes.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6279/

Most IO block offsets have changed in XLP9XX. Update iomap.h to add the
new addresses of different SoC blocks like PIC, SYS, UART etc. that are
needed by the base code.

On XLP9xx, the SoC blocks of other nodes are seen on a PCI bus
corresponding to the node. Update iomap code to reflect this.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6277/

Adds processor ID of XLP 9XX to asm/cpu.h.  Update netlogic/xlp-hal/xlp.h
to add cpu_is_xlp9xx() and to update cpu_is_xlpii() to support XLP 9XX.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6274/

Use the FUSE register to get the list of active cores in the CPU
instead of using the CPU reset register, this is the recommended
method.

Also add code to mask the coremask with the default number of cores
for each processor series.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6275/

On XLPII CPUs, the L1D cache has to be flushed with regular cache
operations before enabling threads in a core.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6276/

No change in logic, the changes are:
* cleanup some whitespace and comments
* remove confusing argument of SYS_CPU_COHERENT_BASE macro
* make the numerical labels in macros consistent
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6273/

Add MSI chip and MSIX chip definitions.

For MSI, we map the link interrupt to a MSI link IRQ which will
do a second level of dispatch based on the MSI status register.

The MSI chip definitions use the MSI enable register to enable
and disable the MSI irqs.

For MSI-X, we split the 32 available MSI-X vectors across the
four PCIe links (8 each). These PIC interrupts generate an IRQ
per link which uses a second level dispatch as well.

The MSI-X chip definition uses the standard functions to enable
and disable interrupts.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6270/

Now that we have a CONFIG_PANIC_TIMEOUT=x setting, remove the
mips settings. The default is 0, which means don't reboot on
panic.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
Acked-by: NShinya Kuribayashi <skuribay@pobox.com>
Signed-off-by: NJason Baron <jbaron@akamai.com>
Cc: benh@kernel.crashing.org
Cc: paulus@samba.org
Cc: mpe@ellerman.id.au
Cc: felipe.contreras@gmail.com
Cc: linux-mips@linux-mips.org
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/d19dc75fca343ec5d9ada75a1400f57330021976.1385418410.git.jbaron@akamai.comSigned-off-by: NIngo Molnar <mingo@kernel.org>

The early_init_devtree() API was removed in linux-next for 3.13 with
commit "mips: use early_init_dt_scan". This causes Netlogic XLP compile
to fail:

arch/mips/netlogic/xlp/setup.c:101: undefined reference to `early_init_devtree'

Add xlp_early_init_devtree() which uses the __dt_setup_arch() to
handle early device tree related initialization to fix this.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Panic() is going to add a \n itself and it's annoying if a panic message rolls
of the screen on a device with no scrollback.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Replace hardcoded CP0 PRId and CP1 FPIR register access masks throughout.
The change does not touch places that use shifted or partial masks.
Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5838/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add a default built-in device tree for XLP2xx SoC. The new file
xlp_fvp.dts has updated entries for I2C and memory.
Signed-off-by: NGanesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5705/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>