1. 05 9月, 2013 3 次提交
  2. 31 8月, 2013 5 次提交
    • V
      ARC: [ASID] Track ASID allocation cycles/generations · 947bf103
      Vineet Gupta 提交于
      This helps remove asid-to-mm reverse map
      
      While mm->context.id contains the ASID assigned to a process, our ASID
      allocator also used asid_mm_map[] reverse map. In a new allocation
      cycle (mm->ASID >= @asid_cache), the Round Robin ASID allocator used this
      to check if new @asid_cache belonged to some mm2 (from prev cycle).
      If so, it could locate that mm using the ASID reverse map, and mark that
      mm as unallocated ASID, to force it to refresh at the time of switch_mm()
      
      However, for SMP, the reverse map has to be maintained per CPU, so
      becomes 2 dimensional, hence got rid of it.
      
      With reverse map gone, it is NOT possible to reach out to current
      assignee. So we track the ASID allocation generation/cycle and
      on every switch_mm(), check if the current generation of CPU ASID is
      same as mm's ASID; If not it is refreshed.
      
      (Based loosely on arch/sh implementation)
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      947bf103
    • V
      ARC: [ASID] activate_mm() == switch_mm() · c6011553
      Vineet Gupta 提交于
      ASID allocation changes/2
      
      Use the fact that switch_mm() and activate_mm() are exactly same code
      now while acknowledging the semantical difference in comment
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      c6011553
    • V
      ARC: [ASID] get_new_mmu_context() to conditionally allocate new ASID · 3daa48d1
      Vineet Gupta 提交于
      ASID allocation changes/1
      
      This patch does 2 things:
      
      (1) get_new_mmu_context() NOW moves mm->ASID to a new value ONLY if it
          was from a prev allocation cycle/generation OR if mm had no ASID
          allocated (vs. before would unconditionally moving to a new ASID)
      
          Callers desiring unconditional update of ASID, e.g.local_flush_tlb_mm()
          (for parent's address space invalidation at fork) need to first force
          the parent to an unallocated ASID.
      
      (2) get_new_mmu_context() always sets the MMU PID reg with unchanged/new
          ASID value.
      
      The gains are:
      - consolidation of all asid alloc logic into get_new_mmu_context()
      - avoiding code duplication in switch_mm() for PID reg setting
      - Enables future change to fold activate_mm() into switch_mm()
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      3daa48d1
    • V
      ARC: [ASID] Refactor the TLB paranoid debug code · 5bd87adf
      Vineet Gupta 提交于
      -Asm code already has values of SW and HW ASID values, so they can be
       passed to the printing routine.
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      5bd87adf
    • V
      ade922f8
  3. 30 8月, 2013 3 次提交
  4. 29 8月, 2013 2 次提交
    • V
      ARC: MMUv4 preps/1 - Fold PTE K/U access flags · 64b703ef
      Vineet Gupta 提交于
      The current ARC VM code has 13 flags in Page Table entry: some software
      (accesed/dirty/non-linear-maps) and rest hardware specific. With 8k MMU
      page, we need 19 bits for addressing page frame so remaining 13 bits is
      just about enough to accomodate the current flags.
      
      In MMUv4 there are 2 additional flags, SZ (normal or super page) and WT
      (cache access mode write-thru) - and additionally PFN is 20 bits (vs. 19
      before for 8k). Thus these can't be held in current PTE w/o making each
      entry 64bit wide.
      
      It seems there is some scope of compressing the current PTE flags (and
      freeing up a few bits). Currently PTE contains fully orthogonal distinct
      access permissions for kernel and user mode (Kr, Kw, Kx; Ur, Uw, Ux)
      which can be folded into one set (R, W, X). The translation of 3 PTE
      bits into 6 TLB bits (when programming the MMU) can be done based on
      following pre-requites/assumptions:
      
      1. For kernel-mode-only translations (vmalloc: 0x7000_0000 to
         0x7FFF_FFFF), PTE additionally has PAGE_GLOBAL flag set (and user
         space entries can never be global). Thus such a PTE can translate
         to Kr, Kw, Kx (as appropriate) and zero for User mode counterparts.
      
      2. For non global entries, the PTE flags can be used to create mirrored
         K and U TLB bits. This is true after commit a950549c
         "ARC: copy_(to|from)_user() to honor usermode-access permissions"
         which ensured that user-space translations _MUST_ have same access
         permissions for both U/K mode accesses so that  copy_{to,from}_user()
         play fair with fault based CoW break and such...
      
      There is no such thing as free lunch - the cost is slightly infalted
      TLB-Miss Handlers.
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      64b703ef
    • V
      ARC: Code cosmetics (Nothing semantical) · 4b06ff35
      Vineet Gupta 提交于
      * reduce editor lines taken by pt_regs
      * ARCompact ISA specific part of TLB Miss handlers clubbed together
      * cleanup some comments
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      4b06ff35
  5. 26 8月, 2013 3 次提交
    • V
      ARC: Entry Handler tweaks: Optimize away redundant IRQ_DISABLE_SAVE · fce16bc3
      Vineet Gupta 提交于
      In the exception return path, for both U/K cases, intr are already
      disabled (for various existing reasons). So when we drop down to
      @restore_regs, we need not redo that.
      
      There was subtle issue - when intr were NOT being disabled for
      ret-to-kernel-but-no-preemption case - now fixed by moving the
      IRQ_DISABLE further up in @resume_kernel_mode.
      
      So what do we gain:
      
      * Shaves off a few insn in return path.
      
      * Eliminates the need for IRQ_DISABLE_SAVE assembler macro for ARCv2
        hence allows for entry code sharing.
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      fce16bc3
    • V
      ARC: Exception Handlers Code consolidation · 37f3ac49
      Vineet Gupta 提交于
      After the recent cleanups, all the exception handlers now have same
      boilerplate prologue code. Move that into common macro.
      
      This reduces readability but helps greatly with sharing / duplicating
      entry code with ARCv2 ISA where the handlers are pretty much the same,
      just the entry prologue is different (due to hardware assist).
      
      Also while at it, add the missing FAKE_RET_FROM_EXCPN calls in couple of
      places to drop down to pure kernel mode (from exception mode) before
      jumping off into "C" code.
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      37f3ac49
    • V
      ARC: Add some .gitignore entries · fe240f11
      Vineet Gupta 提交于
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      fe240f11
  6. 25 8月, 2013 1 次提交
  7. 27 7月, 2013 1 次提交
  8. 10 7月, 2013 1 次提交
    • J
      mm: invoke oom-killer from remaining unconverted page fault handlers · 609838cf
      Johannes Weiner 提交于
      A few remaining architectures directly kill the page faulting task in an
      out of memory situation.  This is usually not a good idea since that
      task might not even use a significant amount of memory and so may not be
      the optimal victim to resolve the situation.
      
      Since 2.6.29's 1c0fe6e3 ("mm: invoke oom-killer from page fault") there
      is a hook that architecture page fault handlers are supposed to call to
      invoke the OOM killer and let it pick the right task to kill.  Convert
      the remaining architectures over to this hook.
      
      To have the previous behavior of simply taking out the faulting task the
      vm.oom_kill_allocating_task sysctl can be set to 1.
      Signed-off-by: NJohannes Weiner <hannes@cmpxchg.org>
      Reviewed-by: NMichal Hocko <mhocko@suse.cz>
      Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
      Acked-by: NDavid Rientjes <rientjes@google.com>
      Acked-by: Vineet Gupta <vgupta@synopsys.com>   [arch/arc bits]
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Jonas Bonn <jonas@southpole.se>
      Cc: Chen Liqin <liqin.chen@sunplusct.com>
      Cc: Lennox Wu <lennox.wu@gmail.com>
      Cc: Chris Metcalf <cmetcalf@tilera.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      609838cf
  9. 05 7月, 2013 1 次提交
  10. 04 7月, 2013 4 次提交
    • J
      mm/ARC: prepare for removing num_physpages and simplify mem_init() · de35e1b8
      Jiang Liu 提交于
      Prepare for removing num_physpages and simplify mem_init().
      Signed-off-by: NJiang Liu <jiang.liu@huawei.com>
      Acked-by: Vineet Gupta <vgupta@synopsys.com>   # for arch/arc
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: Rob Herring <rob.herring@calxeda.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      de35e1b8
    • J
      mm: concentrate modification of totalram_pages into the mm core · 0c988534
      Jiang Liu 提交于
      Concentrate code to modify totalram_pages into the mm core, so the arch
      memory initialized code doesn't need to take care of it.  With these
      changes applied, only following functions from mm core modify global
      variable totalram_pages: free_bootmem_late(), free_all_bootmem(),
      free_all_bootmem_node(), adjust_managed_page_count().
      
      With this patch applied, it will be much more easier for us to keep
      totalram_pages and zone->managed_pages in consistence.
      Signed-off-by: NJiang Liu <jiang.liu@huawei.com>
      Acked-by: NDavid Howells <dhowells@redhat.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: "Michael S. Tsirkin" <mst@redhat.com>
      Cc: <sworddragon2@aol.com>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Chris Metcalf <cmetcalf@tilera.com>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Jeremy Fitzhardinge <jeremy@goop.org>
      Cc: Jianguo Wu <wujianguo@huawei.com>
      Cc: Joonsoo Kim <js1304@gmail.com>
      Cc: Kamezawa Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
      Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      Cc: Marek Szyprowski <m.szyprowski@samsung.com>
      Cc: Mel Gorman <mel@csn.ul.ie>
      Cc: Michel Lespinasse <walken@google.com>
      Cc: Minchan Kim <minchan@kernel.org>
      Cc: Rik van Riel <riel@redhat.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: Tang Chen <tangchen@cn.fujitsu.com>
      Cc: Tejun Heo <tj@kernel.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Wen Congyang <wency@cn.fujitsu.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Yasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com>
      Cc: Yinghai Lu <yinghai@kernel.org>
      Cc: Russell King <rmk@arm.linux.org.uk>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      0c988534
    • J
      mm: enhance free_reserved_area() to support poisoning memory with zero · dbe67df4
      Jiang Liu 提交于
      Address more review comments from last round of code review.
      1) Enhance free_reserved_area() to support poisoning freed memory with
         pattern '0'. This could be used to get rid of poison_init_mem()
         on ARM64.
      2) A previous patch has disabled memory poison for initmem on s390
         by mistake, so restore to the original behavior.
      3) Remove redundant PAGE_ALIGN() when calling free_reserved_area().
      Signed-off-by: NJiang Liu <jiang.liu@huawei.com>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: "Michael S. Tsirkin" <mst@redhat.com>
      Cc: <sworddragon2@aol.com>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Chris Metcalf <cmetcalf@tilera.com>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Jeremy Fitzhardinge <jeremy@goop.org>
      Cc: Jianguo Wu <wujianguo@huawei.com>
      Cc: Joonsoo Kim <js1304@gmail.com>
      Cc: Kamezawa Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
      Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      Cc: Marek Szyprowski <m.szyprowski@samsung.com>
      Cc: Mel Gorman <mel@csn.ul.ie>
      Cc: Michel Lespinasse <walken@google.com>
      Cc: Minchan Kim <minchan@kernel.org>
      Cc: Rik van Riel <riel@redhat.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: Tang Chen <tangchen@cn.fujitsu.com>
      Cc: Tejun Heo <tj@kernel.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Wen Congyang <wency@cn.fujitsu.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Yasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com>
      Cc: Yinghai Lu <yinghai@kernel.org>
      Cc: Russell King <rmk@arm.linux.org.uk>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      dbe67df4
    • J
      mm: change signature of free_reserved_area() to fix building warnings · 11199692
      Jiang Liu 提交于
      Change signature of free_reserved_area() according to Russell King's
      suggestion to fix following build warnings:
      
        arch/arm/mm/init.c: In function 'mem_init':
        arch/arm/mm/init.c:603:2: warning: passing argument 1 of 'free_reserved_area' makes integer from pointer without a cast [enabled by default]
          free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, 0, NULL);
          ^
        In file included from include/linux/mman.h:4:0,
                         from arch/arm/mm/init.c:15:
        include/linux/mm.h:1301:22: note: expected 'long unsigned int' but argument is of type 'void *'
         extern unsigned long free_reserved_area(unsigned long start, unsigned long end,
      
         mm/page_alloc.c: In function 'free_reserved_area':
      >> mm/page_alloc.c:5134:3: warning: passing argument 1 of 'virt_to_phys' makes pointer from integer without a cast [enabled by default]
         In file included from arch/mips/include/asm/page.h:49:0,
                          from include/linux/mmzone.h:20,
                          from include/linux/gfp.h:4,
                          from include/linux/mm.h:8,
                          from mm/page_alloc.c:18:
         arch/mips/include/asm/io.h:119:29: note: expected 'const volatile void *' but argument is of type 'long unsigned int'
         mm/page_alloc.c: In function 'free_area_init_nodes':
         mm/page_alloc.c:5030:34: warning: array subscript is below array bounds [-Warray-bounds]
      
      Also address some minor code review comments.
      Signed-off-by: NJiang Liu <jiang.liu@huawei.com>
      Reported-by: NArnd Bergmann <arnd@arndb.de>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: "Michael S. Tsirkin" <mst@redhat.com>
      Cc: <sworddragon2@aol.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Chris Metcalf <cmetcalf@tilera.com>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Jeremy Fitzhardinge <jeremy@goop.org>
      Cc: Jianguo Wu <wujianguo@huawei.com>
      Cc: Joonsoo Kim <js1304@gmail.com>
      Cc: Kamezawa Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
      Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      Cc: Marek Szyprowski <m.szyprowski@samsung.com>
      Cc: Mel Gorman <mel@csn.ul.ie>
      Cc: Michel Lespinasse <walken@google.com>
      Cc: Minchan Kim <minchan@kernel.org>
      Cc: Rik van Riel <riel@redhat.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: Tang Chen <tangchen@cn.fujitsu.com>
      Cc: Tejun Heo <tj@kernel.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Wen Congyang <wency@cn.fujitsu.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Yasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com>
      Cc: Yinghai Lu <yinghai@kernel.org>
      Cc: Russell King <rmk@arm.linux.org.uk>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      11199692
  11. 29 6月, 2013 2 次提交
  12. 28 6月, 2013 2 次提交
  13. 27 6月, 2013 5 次提交
    • V
      baadb8fd
    • P
      arc: delete __cpuinit usage from all arc files · ce759956
      Paul Gortmaker 提交于
      The __cpuinit type of throwaway sections might have made sense
      some time ago when RAM was more constrained, but now the savings
      do not offset the cost and complications.  For example, the fix in
      commit 5e427ec2 ("x86: Fix bit corruption at CPU resume time")
      is a good example of the nasty type of bugs that can be created
      with improper use of the various __init prefixes.
      
      After a discussion on LKML[1] it was decided that cpuinit should go
      the way of devinit and be phased out.  Once all the users are gone,
      we can then finally remove the macros themselves from linux/init.h.
      
      Note that some harmless section mismatch warnings may result, since
      notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
      are flagged as __cpuinit  -- so if we remove the __cpuinit from
      arch specific callers, we will also get section mismatch warnings.
      As an intermediate step, we intend to turn the linux/init.h cpuinit
      content into no-ops as early as possible, since that will get rid
      of these warnings.  In any case, they are temporary and harmless.
      
      This removes all the arch/arc uses of the __cpuinit macros from
      all C files.  Currently arc does not have any __CPUINIT used in
      assembly files.
      
      [1] https://lkml.org/lkml/2013/5/20/589
      
      Cc: Vineet Gupta <vgupta@synopsys.com>
      Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      ce759956
    • V
      ARC: [tlb-miss] Fix bug with CONFIG_ARC_DBG_TLB_MISS_COUNT · dc81df24
      Vineet Gupta 提交于
      LOAD_FAULT_PTE macro is expected to set r2 with faulting vaddr.
      However in case of CONFIG_ARC_DBG_TLB_MISS_COUNT, it was getting
      clobbered with statistics collection code.
      
      Fix latter by using a different register.
      
      Note that only I-TLB Miss handler was potentially affected.
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      dc81df24
    • V
      ARC: [tlb-miss] Extraneous PTE bit testing/setting · c3e757a7
      Vineet Gupta 提交于
      * No need to check for READ access in I-TLB Miss handler
      
      * Redundant PAGE_PRESENT update in PTE
      
      Post TLB entry installation, in updating PTE for software accessed/dity
      bits, no need to update PAGE_PRESENT since it will already be set.
      Infact the entry won't have installed if !PAGE_PRESENT.
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      c3e757a7
    • V
      ARC: Adjustments for gcc 4.8 · 5a45da02
      Vineet Gupta 提交于
      * DWARF unwinder related
        + Force DWARF2 compliant .debug_frame (gcc 4.8 defaults to DWARF4
          which kernel unwinder can't grok).
        + Discard the additional .eh_frame generated
        + Discard the dwarf4 debug info generated by -gdwarf-2 for normal
          no debug case
      
      * 4.8 already uses arc600 multilibs for -mno-mpy
      
      * switch to using uclibc compiler (to get -mmedium-calls and -mno-sdata)
        and also since buildroot can only use 1 toolchain
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      5a45da02
  14. 26 6月, 2013 4 次提交
    • C
      i2c-designware: make SDA hold time configurable · 9803f868
      Christian Ruppert 提交于
      This patch makes the SDA hold time configurable through device tree.
      Signed-off-by: NChristian Ruppert <christian.ruppert@abilis.com>
      Signed-off-by: NPierrick Hascoet <pierrick.hascoet@abilis.com>
      Acked-by: Vineet Gupta <vgupta@synopsys.com> for arch/arc bits
      Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      9803f868
    • V
      ARC: Setup Vector Table Base in early boot · 05b016ec
      Vineet Gupta 提交于
      Otherwise early boot exceptions such as instructions errors due to
      configuration mismatch between kernel and hardware go off to la-la land,
      as opposed to hitting the handler and panic()'ing properly.
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      05b016ec
    • V
      ARC: Remove explicit passing around of ECR · 38a9ff6d
      Vineet Gupta 提交于
      With ECR now part of pt_regs
      
      * No need to propagate from lowest asm handlers as arg
      * No need to save it in tsk->thread.cause_code
      * Avoid bit chopping to access the bit-fields
      
      More code consolidation, cleanup
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      38a9ff6d
    • V
      ARC: pt_regs update #5: Use real ECR for pt_regs->event vs. synth values · 502a0c77
      Vineet Gupta 提交于
      pt_regs->event was set with artificial values to identify the low level
      system event (syscall trap / breakpoint trap / exceptions / interrupts)
      
      With r8 saving out of the way, the full word can be used to save real
      ECR (Exception Cause Register) which helps idenify the event naturally,
      including additional info such as cause code, param.
      Only for Interrupts, where ECR is not applicable, do we resort to
      synthetic non ECR values.
      
      SAVE_ALL_TRAP/EXCEPTIONS can now be merged as they both use ECR with
      different runtime values.
      
      The ptrace helpers now use the sub-fields of ECR to distinguish the
      events (e.g. vector 0x25 is trap, param 0 is syscall...)
      
      The following benefits will follow:
      
      (1) This centralizes the location of where ECR is saved and will allow
          the cleanup of task->thread.cause_code ECR placeholder which is set
          in non-uniform way. Then ARC VM code can safely rely on it being
          there for purpose of finer grained VM_EXEC dcache flush (based on
          exec fault: I-TLB Miss)
      
      (2) Further, ECR being passed around from low level handlers as arg can
          be eliminated as it is part of standard reg-file in pt_regs
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      502a0c77
  15. 22 6月, 2013 3 次提交
    • V
      ARC: stop using pt_regs->orig_r8 · 352c1d95
      Vineet Gupta 提交于
      Historically, pt_regs have had orig_r8, an overloaded container for
        (1) backup copy of r8 (syscall number Trap Exceptions)
        (2) additional system state: (syscall/Exception/Interrupt)
      
      There is no point in keeping (1) since syscall number is never clobbered
      in-place, in pt_regs, unlike r0 which duals as first syscall arg as well
      as syscall return value and in case of syscall restart, the orig arg0
      needs restoring (from orig_r0)  after having been updated in-place with
      syscall ret value.
      
      This further paves way to convert (2) to contain ECR itself (rather than
      current madeup values)
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      352c1d95
    • V
      ARC: pt_regs update #4: r25 saved/restored unconditionally · 359105bd
      Vineet Gupta 提交于
      (This is a VERY IMP change for low level interrupt/exception handling)
      
      -----------------------------------------------------------------------
      WHAT
      -----------------------------------------------------------------------
      * User 25 now saved in pt_regs->user_r25 (vs. tsk->thread_info.user_r25)
      
      * This allows Low level interrupt code to unconditionally save r25
        (vs. the prev version which would only do it for U->K transition).
        Ofcourse for nested interrupts, only the pt_regs->user_r25 of
        bottom-most frame is useful.
      
      * simplifies the interrupt prologue/epilogue
      
      * Needed for ARCv2 ISA code and done here to keep design similar with
        ARCompact event handling
      
      -----------------------------------------------------------------------
      WHY
      -------------------------------------------------------------------------
      With CONFIG_ARC_CURR_IN_REG, r25 is used to cache "current" task pointer
      in kernel mode. So when entering kernel mode from User Mode
      - user r25 is specially safe-kept (it being a callee reg is NOT part of
        pt_regs which are saved by default on each interrupt/trap/exception)
      - r25 loaded with current task pointer.
      
      Further, if interrupt was taken in kernel mode, this is skipped since we
      know that r25 already has valid "current" pointer.
      
      With 2 level of interrupts in ARCompact ISA, detecting this is difficult
      but still possible, since we could be in kernel mode but r25 not already saved
      (in fact the stack itself might not have been switched).
      
      A. User mode
      B. L1 IRQ taken
      C. L2 IRQ taken (while on 1st line of L1 ISR)
      
      So in #C, although in kernel mode, r25 not saved (infact SP not
      switched at all)
      
      Given that ARcompact has manual stack switching, we could use a bit of
      trickey - The low level code would make sure that SP is only set to kernel
      mode value at the very end (after saving r25). So a non kernel mode SP,
      even if in kernel mode, meant r25 was NOT saved.
      
      The same paradigm won't work in ARCv2 ISA since SP is auto-switched so
      it's setting can't be delayed/constrained.
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      359105bd
    • V
      ARC: K/U SP saved from one location in stack switching macro · ba3558c7
      Vineet Gupta 提交于
      This paves way for further simplifications.
      
      There's an overhead of 1 insn for the non-common case of interrupt taken
      from kernel mode.
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      ba3558c7
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