Adds a new cpu type for the JZ4740 to the Linux MIPS architecture code.
It also adds the iomem addresses for the different components found on
a JZ4740 SoC.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1464/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

* Rename camel-case InitTLBStart_addr to octeon_bootloader_entry_addr.

* Convert calls to cvmx_read64_uint32(), to simple pointer
  dereferences.

* Set proper ebase.

* Don't confuse coreid and cpu numbers.

* Try to maintain consistent bootloader coremask.

* Update the signature and boot_init_vector of supported bootloaders.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1491/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

MSI IRQ numbers are allocated dynamically, so there is no reason to
have all these static definitions.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1487/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

au1000_eth uses firmware calls to get a valid MAC address, and changes
it depending on platform device id.  This patch moves this logic out of
the driver into the platform device registration part, where boards with
supported chips can use whatever firmware interface they need; the default
implementation maintains compatibility with existing, YAMON-based firmware.
Tested-by: NWolfgang Grandegger <wg@denx.de>
Acked-by: NFlorian Fainelli <florian@openwrt.org>
Signed-off-by: NManuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: netdev@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1481/Acked-by: NDavid S. Miller <davem@davemloft.net>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Remove the CONFIG_SOC_AU1X00 Kconfig symbol since its job can also be done
by MACH_ALCHEMY, now renamed to MIPS_ALCHEMY.
Signed-off-by: NManuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/1461/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add support for the external T-cache interface. Allow for platform
independent size probing from 512KB to 8MB in powers of two.
Signed-off-by: NRicardo Mendoza <ricmm@gentoo.org>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1477/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Based somewhat on the PPC implementation.

32-bit processes have the heap randomized in an 8MB space, 256MB for
64-bit processes.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1479/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Fairly straight forward: For 32-bit address spaces randomize within a
16MB space, for 64-bit within a 256MB space.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1480/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Don't duplicate worthless lines.
Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1390/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Don't duplicate worthless lines.
Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1389/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Although all EMMAxxx SoCs can support IP2 and IP3 hardware interrupts,
current EMMA2RH plat_irq_dispatch() supports IP2 only.  We can make it
configurable in the future, but for the time being, would like to make
things explicitly allcated to IP2 in accordance with plat_irq_dispatch().
Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1388/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

For historical reasons, we used to put MIPS CPU IRQs behind SoC-specific
IRQs in the queue, and have been using CPU_IRQ_BASE as MIPS_CPU_IRQ_BASE.
In recent years, however, we've brought it back to normal order, and now
CPU_IRQ_BASE just redefines the generic MIPS_CPU_IRQ_BASE.

At the same time, NUM_CPU_IRQ is also removed as useless.
Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1387/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

OCTEON implements __builtin_popcount with a single instruction, so lets use it.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Cc: David Daney <ddaney@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/1431/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Some MIPS ISA processor varients can do hweight operations
efficiently.

Split arch_hweight.h into a seperate file, and implement the
operations with __builtin_popcount{,ll} if supported.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Cc: David Daney <ddaney@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/1430/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

CONFIG_MTD_PMC_MSP_RAMROOT doesn't exist in Kconfig, therefore removing all
references for it from the source code.
Signed-off-by: NChristoph Egger <siccegge@cs.fau.de>
To:     Ralf Baechle <ralf@linux-mips.org>,
        Yoichi Yuasa <yuasa@linux-mips.org>, linux-mips@linux-mips.org,
        linux-kernel@vger.kernel.org
Cc:     vamos@i4.informatik.uni-erlangen.de
Acked-by: NShane McDonald <mcdonald.shane@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/1375/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

CONFIG_MTD_PB1550_BOOT, CONFIG_MTD_PB1550_USER doesn't exist in
Kconfig, therefore removing all references for it from the source
code.
Signed-off-by: NChristoph Egger <siccegge@cs.fau.de>
To: Manuel Lauss <manuel.lauss@gmail.com>,
To: linux-mips@linux-mips.org
To: linux-kernel@vger.kernel.org
Cc: vamos@i4.informatik.uni-erlangen.de
Patchwork: https://patchwork.linux-mips.org/patch/1370/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/1504/

Correct ASIC device register names and addresses for USB devices.
Signed-off-by: NDavid VomLehn <dvomlehn@cisco.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1258/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Replace phys_to_dma()/dma_to_phys() looping algorithm with an O(1) algorithm
The approach taken is inspired by the sparse memory implementation: take a
certain number of high-order bits off the address them, use this as an
index into a table containing an offset to the desired address and add
it to the original value. There is a table for mapping physical addresses
to DMA addresses and another one for the reverse mapping. The table sizes
depend on how fine-grained the mappings need to be; Coarser granularity
less to smaller tables.  On a processor with 32-bit physical and DMA
addresses, with 4 MIB granularity, memory usage is two 2048-byte arrays.
Each 32-byte cache line thus covers 64 MiB of address space.

Also, renames phys_to_bus() to phys_to_dma() and bus_to_phys() to
dma_to_phys() to align with kernel usage.

[Ralf: Fixed silly build breakage due to stackoverflow warning caused by
huge array on stack.]
Signed-off-by: NDavid VomLehn <dvomlehn@cisco.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1257/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The include is unecessary and will when building the IP35 result in
recursive header inclusion spaghetti.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

With SLAB, it works without ARCH_KMALLOC_MINALIGN, but with SLOB/SLUB,
ARCH_KMALLOC_MINALIGN is required to ensure alignment of kmalloced
buffer.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1248/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

For 64-bit, we must use DADDU and DSUBU.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1483/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

As a relativly new ABI N32 should only have received the getdents64(2) but
instead it only had getdents(2).  This was noticed as a performance anomaly
in glibc.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

When trying to netboot a Linksys WRT54GS WLAN router, the bootup fails,
because of following error message:

...
[    0.424000] b44: b44.c:v2.0
[    0.424000] b44: Invalid MAC address found in EEPROM
[    0.432000] b44 ssb0:1: Problem fetching invariants of chip,aborting
[    0.436000] b44: probe of ssb0:1 failed with error -22
...

The router uses a CFE bootloader, but most of the needed environment
variables for network card initialization, are not available from CFE
via printenv and even though not via cfe_getenv().
The required environment variables are saved in a special partition
in flash memory. The attached patch implement nvram_getenv and enables
bootup via NFS root on my router.

Most of the patch is extracted from the OpenWrt subversion repository and
stripped down and cleaned up to just fix this issue.

[Ralf: sorted out header file inclusions.  Lots of unneded headers and such
that should have been included.]
Signed-off-by: NWaldemar Brodkorb <wbx@openadk.org>
Reviewed-by: NPhil Sutter <phil@nwl.cc>
To: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: http://patchwork.linux-mips.org/patch/1359/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Split the low-level sleepcode into per-cpu functions instead of
relying on compile-time-defined cpu type.
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/1281/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The return value of gpio_to_irq() is not a pointer but an integer.
Signed-off-by: NYoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/1280/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This fixes a typo on the AR7_RESET_PERIPHERAL define.
Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/1247/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

GCC's __builtin_prefetch() was introduced a long time ago, all
supported GCC versions have it.  Lets do what the big boys up in
linux/prefetch.h do, except we use '1' as the third parameter to
provoke 'PREF 0,...'  and 'PREF 1,...' instead of other prefetch
hints.

This allows for better code generation.  In theory the existing
embedded asm could be optimized, but the compiler has these builtins,
so there is really no point.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/1235/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This is too generic a name, so prefix it with BCM63XX_ to avoid potential
namespace clashes when including <asm/gpio.h>.
Signed-off-by: NFlorian Fainelli <ffainelli@freebox.fr>
To:     linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/1171/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NArnaud Patard <apatard@mandriva.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/1163/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add a sysdev for DBDMA PM.
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/1119/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Use a sysdev to implement PM methods for the Au1000 interrupt controllers.
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/1114/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Loongson doesn't support MIPSR2, therefore, MIPSR2 vectored interrupts
(cpu_has_vint) and MIPSR2 external interrupt controller mode
(cpu_has_veic) are 0.
Signed-off-by: NWu Zhangjin <wuzhangjin@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/1112/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The only way the debugger can handle a trap in inside rcu_lock,
notify_die, or atomic_notifier_call_chain without a recursive fault is
to have a low level "first opportunity handler" do_trap_or_bp() handler.

Generally this will be something the vast majority of folks will not
need, but for those who need it, it is added as a kernel .config
option called KGDB_LOW_LEVEL_TRAP.

Also added was a die notification for oops such that kdb can catch an
oops for analysis.

There appeared to be no obvious way to pass the struct pt_regs from
the original exception back to the stack back tracer, so a special
case was added to show_stack() for when kdb is active because you
generally desire to generally look at the back trace of the original
exception.
Signed-off-by: NJason Wessel <jason.wessel@windriver.com>
Acked-by: NRalf Baechle <ralf@linux-mips.org>

In preparation for removing volatile from the atomic_t definition, this
patch adds a volatile cast to all the atomic read functions.
Signed-off-by: NAnton Blanchard <anton@samba.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

    
    In the FPU emulator code of the MIPS, the Cause bits of the FCSR register
    are not currently writeable by the ctc1 instruction.  In odd corner cases,
    this can cause problems.  For example, a case existed where a divide-by-zero
    exception was generated by the FPU, and the signal handler attempted to
    restore the FPU registers to their state before the exception occurred.  In
    this particular setup, writing the old value to the FCSR register would
    cause another divide-by-zero exception to occur immediately.  The solution
    is to change the ctc1 instruction emulator code to allow the Cause bits of
    the FCSR register to be writeable.  This is the behaviour of the hardware
    that the code is emulating.
    
    This problem was found by Shane McDonald, but the credit for the fix goes
    to Kevin Kissell.  In Kevin's words:
    
    I submit that the bug is indeed in that ctc_op:  case of the emulator.  The
    Cause bits (17:12) are supposed to be writable by that instruction, but the
    CTC1 emulation won't let them be updated by the instruction.  I think that
    actually if you just completely removed lines 387-388 [...] things would
    work a good deal better.  At least, it would be a more accurate emulation of
    the architecturally defined FPU.  If I wanted to be really, really pedantic
    (which I sometimes do), I'd also protect the reserved bits that aren't
    necessarily writable.
Signed-off-by: NShane McDonald <mcdonald.shane@gmail.com>
    To: anemo@mba.ocn.ne.jp
    To: kevink@paralogos.com
    To: sshtylyov@mvista.com
    Patchwork: http://patchwork.linux-mips.org/patch/1205/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

---

Signed-off-by: NAndreas Dilger <adilger@dilger.ca>
Acked-by: NKOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>

Signed-off-by: NWu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/1106/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>