- 06 1月, 2015 4 次提交
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由 Hariprasad Shenai 提交于
This patch cleanups all TP, MPS and TCAM related macros/register defines that are defined in t4_regs.h and the affected files Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
This patch cleanups all MC, MA and CIM related macros/register defines that are defined in t4_regs.h and the affected files. Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
This patch cleansup remaining SGE related macros/register defines and all PCI related ones that are defined in t4_regs.h and the affected files. Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
This patch cleanups all SGE related macros/register defines that are defined in t4_regs.h and the affected files. Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 10 12月, 2014 2 次提交
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由 Hariprasad Shenai 提交于
Add new Common Code facilities for calculating T5 BAR2 Offsets for SGE Queue Registers. This new code can handle situations where Queues Per Page * SGE BAR2 Queue Register Area Size > Page Size Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
Add sge_vf_eq_qpp and sge_vf_iq_qpp to (struct sge_params), initialize sge_queues_per_page and sge_vf_qpp in t4vf_get_sge_params(), add new t4vf_prep_adapter() which initializes basic adapter parameters. Grab both SGE_EGRESS_QUEUES_PER_PAGE_VF and SGE_INGRESS_QUEUES_PER_PAGE_VF for VF Drivers since we need both to calculate the User Doorbell area offsets for Egress and Ingress Queues. Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 11 11月, 2014 2 次提交
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由 Hariprasad Shenai 提交于
T5 introduces the ability to have separate Packing and Padding Boundaries for SGE DMA transfers from the chip to Host Memory. This change set takes advantage of that to set up a smaller Padding Boundary to conserve PCI Link and Memory Bandwidth with T5. Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
Various patches have ended up changing the style of the symbolic macros/register to different style. As a result, the current kernel.org files are a mix of different macro styles. Since this macro/register defines is used by different drivers a few patch series have ended up adding duplicate macro/register define entries with different styles. This makes these register define/macro files a complete mess and we want to make them clean and consistent. This patch cleans up a part of it. Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 10 10月, 2014 1 次提交
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由 Hariprasad Shenai 提交于
Update the lso length for T5 adapter and fix PIDX_T5 macro Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 29 9月, 2014 2 次提交
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由 Hariprasad Shenai 提交于
Based on original work by Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
Use BAR2 GTS for T5. If we are on T4 use the old doorbell mechanism; otherwise ue the new BAR2 mechanism. Use BAR2 doorbells for refilling FL's. Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 02 9月, 2014 1 次提交
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由 Hariprasad Shenai 提交于
Fixes few register access for both T4 and T5. PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS & PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS is T4 only register don't let T5 access them. For T5 MA_PARITY_ERROR_STATUS2 is additionally read. MPS_TRC_RSS_CONTROL is T4 only register, for T5 use MPS_T5_TRC_RSS_CONTROL. Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 22 7月, 2014 1 次提交
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由 Hariprasad Shenai 提交于
Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 16 7月, 2014 1 次提交
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由 Hariprasad Shenai 提交于
This commit enhances the iwarp driver to optionally keep a log of rdma work request timining data for kernel mode QPs. If iw_cxgb4 module option c4iw_wr_log is set to non-zero, each work request is tracked and timing data maintained in a rolling log that is 4096 entries deep by default. Module option c4iw_wr_log_size_order allows specifing a log2 size to use instead of the default order of 12 (4096 entries). Both module options are read-only and must be passed in at module load time to set them. IE: modprobe iw_cxgb4 c4iw_wr_log=1 c4iw_wr_log_size_order=10 The timing data is viewable via the iw_cxgb4 debugfs file "wr_log". Writing anything to this file will clear all the timing data. Data tracked includes: - The host time when the work request was posted, just before ringing the doorbell. The host time when the completion was polled by the application. This is also the time the log entry is created. The delta of these two times is the amount of time took processing the work request. - The qid of the EQ used to post the work request. - The work request opcode. - The cqe wr_id field. For sq completions requests this is the swsqe index. For recv completions this is the MSN of the ingress SEND. This value can be used to match log entries from this log with firmware flowc event entries. - The sge timestamp value just before ringing the doorbell when posting, the sge timestamp value just after polling the completion, and CQE.timestamp field from the completion itself. With these three timestamps we can track the latency from post to poll, and the amount of time the completion resided in the CQ before being reaped by the application. With debug firmware, the sge timestamp is also logged by firmware in its flowc history so that we can compute the latency from posting the work request until the firmware sees it. Signed-off-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 02 7月, 2014 2 次提交
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由 Hariprasad Shenai 提交于
Rip out a bunch of redundant PCI-E Memory Window Read/Write routines, collapse the more general purpose routines into a single routine thereby eliminating the need for a large stack frame (and extra data copying) in the outer routine, change everything to use the improved routine t4_memory_rw. Based on origninal work by Casey Leedom <leedom@chelsio.com> and Steve Wise <swise@opengridcomputing.com> Signed-off-by: NCasey Leedom <leedom@chelsio.com> Signed-off-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
Use the firmware interface to get the BAR0 value since we really don't want to use the PCI-E Configuration Space Backdoor access which is owned by the firmware. Set up PCI-E Memory Window registers using the true values programmed into BAR registers. When the PF4 "Master Function" is exported to a Virtual Machine, the values returned by pci_resource_start() will be for the synthetic PCI-E Configuration Space and not the real addresses. But we need to program the PCI-E Memory Window address decoders with the real addresses that we're going to be using in order to have accesses through the Memory Windows work. Based on origninal work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NCasey Leedom <leedom@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 23 6月, 2014 1 次提交
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由 Anish Bhatt 提交于
Signed-off-by: NAnish Bhatt <anish@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 14 3月, 2014 2 次提交
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由 Kumar Sanghvi 提交于
Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NKumar Sanghvi <kumaras@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Kumar Sanghvi 提交于
Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NKumar Sanghvi <kumaras@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 23 12月, 2013 2 次提交
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由 Kumar Sanghvi 提交于
Adds API cxgb4_select_ntuple so as to enable Upper Level Drivers to correctly calculate the tuple fields. Adds constant definitions for TP_VLAN_PRI_MAP for the Compressed Filter Tuple field widths and structures and uses them. Also, the CPL Parameters field for T5 is 40 bits so we need to prototype cxgb4_select_ntuple() to calculate and return u64 values. Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NKumar Sanghvi <kumaras@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Kumar Sanghvi 提交于
We were creating LE Workaround Server Filters without specifying IPPROTO_TCP (6) in the filters (when F_PROTOCOL is set in TP_VLAN_PRI_MAP). This meant that UDP packets with matching IP Addresses/Ports would get caught up in the filter and be delivered to ULDs like iw_cxgb4. So, include the protocol information in the server filter properly. Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NKumar Sanghvi <kumaras@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 04 12月, 2013 2 次提交
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由 Hariprasad Shenai 提交于
Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 14 3月, 2013 2 次提交
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由 Vipul Pandya 提交于
Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Santosh Rastapur 提交于
Signed-off-by: NSantosh Rastapur <santosh@chelsio.com> Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 20 12月, 2012 3 次提交
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由 Vipul Pandya 提交于
Retries active opens for INUSE errors. Logs any active ofld_connect_wr error replies. Sends ofld_connect_wr on same ctrlq. It needs to go on the same control txq as regular CPL active/passive messages. Retries on active open replies with EADDRINUSE. Uses active open fw wr only if active filter region is set. Adds stat for ofld_connect_wr failures. This patch also adds debugfs file to show endpoints. Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NRoland Dreier <roland@purestorage.com>
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由 Vipul Pandya 提交于
It enables establishing active open connection using fw_ofld_connection work request when cpl_act_open_rpl says TCAM full error which may be because of LE hash collision. Current support is only for IPv4 active open connections. Sets ntuple bits in active open requests. For T4 firmware greater than 1.4.10.0 ntuple bits are required to be set. Adds nocong and enable_ecn module parameter options. Signed-off-by: NVipul Pandya <vipul@chelsio.com> [ Move all FW return values to t4fw_api.h. - Roland ] Signed-off-by: NRoland Dreier <roland@purestorage.com>
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由 Vipul Pandya 提交于
It supports establishing passive open connection through firmware filter work request. Passive open connection will go through this path as now instead of listening server we create a server filter which will redirect the incoming SYN packet to the offload queue. It divides filter region into regular filters and server filter portion. It introduces new server filter region which will be exclusively used for creating server filters. This region will not overlap with regular filter region. It provides new API cxgb4_alloc_sftid in LLD for getting stid in case of LE hash collision path. This new stid will be used to open server filter in the filter region. Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NRoland Dreier <roland@purestorage.com>
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- 27 11月, 2012 1 次提交
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由 Naresh Kumar Inna 提交于
This patch contains updates to firmware/hardware header files shared between csiostor and cxgb4/cxgb4vf, and the resulting changes to the cxgb4/cxgb4vf source files. Signed-off-by: NNaresh Kumar Inna <naresh@chelsio.com> Cc: David Miller <davem@davemloft.net> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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- 28 9月, 2012 4 次提交
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由 Vipul Pandya 提交于
This patch adds a new common code routine to upgrade an adapter's firmware. This routine handles all of the complexities of working with the the existing adapter firmware in order to quiesce the adapter and uP, etc. For an automatic upgrade it will send a HELLO command to check if cxgb4 want/can upgrade firmware, i.e. if cxgb4 is MASTER and has newer firmware that it wants to load and call the new common code routine t4_fw_upgrade. Note that it should not issue a RESET command after a successful firmware upgrade. Signed-off-by: NJay Hernandez <jay@chelsio.com> Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Vipul Pandya 提交于
In case if user defined configuration file at /lib/firmware/cxgb4/t4-config.txt location and also factory default configuration file written to FLASH are not present then driver will use hardwired configuration settings. Signed-off-by: NJay Hernandez <jay@chelsio.com> Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Vipul Pandya 提交于
Starting with T4 firmware version 1.3.11.0 the firmware now supports device configuration via a Firmware Configuration File. The Firmware Configuration File was primarily developed in order to centralize all of the configuration, resource allocation, etc. for Unified Wire operation where multiple Physical / Virtual Function Drivers would be using a T4 adapter simultaneously. The Firmware Configuration file can live in three locations as shown below in order of precedence. 1) User defined configuration file: /lib/firmware/cxgb4/t4-config.txt 2) Factory Default configuration file written to FLASH within the manufacturing process. 3) Hardwired driver configuration. Signed-off-by: NJay Hernandez <jay@chelsio.com> Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Vipul Pandya 提交于
This patch adds new enums and macros to enable T4 configuration file support. It also removes duplicate macro definitions. It fixes the build failure in cxgb4vf driver introduced because of old macro definition removal. It also performs SGE initialization based on T4 configuration file is provided or not. If it is provided then it uses the parameters provided in it otherwise it uses hard coded values. Signed-off-by: NJay Hernandez <jay@chelsio.com> Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 06 9月, 2012 1 次提交
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由 Vipul Pandya 提交于
Removed duplicate definition for SGE_PF_KDOORBELL, SGE_INT_ENABLE3, PCIE_MEM_ACCESS_OFFSET registers. Moved the register field definitions around the register definition. Signed-off-by: NSantosh Rastapur <santosh@chelsio.com> Signed-off-by: NVipul Pandya <vipul@chelsio.com> Reviewed-by: NSivakumar Subramani <sivasu@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 19 5月, 2012 1 次提交
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由 Vipul Pandya 提交于
recover LLD EQs for DB drop interrupts. This includes adding a new db_lock, a spin lock disabling BH too, used by the recovery thread and the ring_tx_db() paths to allow db drop recovery. Clean up initial DB avoidance code. Add read_eq_indices() - this allows the LLD to use the PCIe mw to efficiently read hw eq contexts. Add cxgb4_sync_txq_pidx() - called by iw_cxgb4 to sync up the sw/hw pidx value. Add flush_eq_cache() and cxgb4_flush_eq_cache(). This allows iw_cxgb4 to flush the sge eq context cache before beginning db drop recovery. Add module parameter, dbfoifo_int_thresh, to allow tuning the db interrupt threshold value. Add dbfifo_int_thresh to cxgb4_lld_info so iw_cxgb4 knows the threshold. Add module parameter, dbfoifo_drain_delay, to allow tuning the amount of time delay between DB FULL and EMPTY upcalls to iw_cxgb4. Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NRoland Dreier <roland@purestorage.com>
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- 11 8月, 2011 1 次提交
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由 Jeff Kirsher 提交于
Moves the drivers for the Chelsio chipsets into drivers/net/ethernet/chelsio/ and the necessary Kconfig and Makefile changes. CC: Divy Le Ray <divy@chelsio.com> CC: Dimitris Michailidis <dm@chelsio.com> CC: Casey Leedom <leedom@chelsio.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 03 8月, 2010 1 次提交
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由 Dimitris Michailidis 提交于
Get info about the availability of Tx on-chip queues from FW and if they are supported set up a memory window for them. iw_cxgb4 will be using them. Move the existing window setup later in the init sequence, after we have collected the new info. Signed-off-by: NDimitris Michailidis <dm@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 29 6月, 2010 1 次提交
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由 Casey Leedom 提交于
Add new macros and definitions for hardware constants. Signed-off-by: Casey Leedom Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 19 6月, 2010 1 次提交
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由 Dimitris Michailidis 提交于
Handle the larger flash memories on newer boards: - get the size and number of sectors by probing the flash - writes and erases can take longer, adjust the timeouts for these operations - the FW image can be at different locations depending on flash size, find its location dynamically as well. Signed-off-by: NDimitris Michailidis <dm@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 02 4月, 2010 1 次提交
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由 Dimitris Michailidis 提交于
Signed-off-by: NDimitris Michailidis <dm@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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