1. 18 10月, 2012 1 次提交
  2. 06 9月, 2012 3 次提交
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      drm/i915: no longer call drm_helper_resume_force_mode · 9dc10f37
      Daniel Vetter 提交于
      Since this only calls crtc helper functions, of which a shocking
      amount are NULL.
      
      Now the curious thing is how the new modeset code worked with this
      function call still present:
      
      Thanks to the hw state readout and the suspend fixes to properly
      quiescent the register state, nothing is actually enabled at resume
      (if the bios doesn't set up anything). Which means resume_force_mode
      doesn't actually do anything and hence nothing blows up at resume
      time.
      
      The other reason things do work is that the fbcon layer has it's own
      resume notifier callback, which restores the mode. And thanks to the
      force vt switch at suspend/resume, that then forces X to restore it's
      own mode.
      
      Hence everything still worked (as long as the bios doesn't enable
      anything). And we can just kill the call to resume_force_mode.
      
      The upside of both this patch and the preceeding patch to quiescent
      the modeset state is that our resume path is much simpler:
      - We now longer restore bogus register values (which most often would
        enable the backlight a bit and a few ports), causing flickering.
      - We now longer call resume_force_mode to restore a mode that the
        fbcon layer would overwrite right away anyway.
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      9dc10f37
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      drm/i915: disable all crtcs at suspend time · a261b246
      Daniel Vetter 提交于
      We need this to avoid confusing the hw state readout code with the cpt
      pch plls at resume time: We'd read the new pipe state (which is
      disabled), but still believe that we have a life pll connected to that
      pipe (from before the suspend). Hence properly disable pipes to clear
      out all the residual state.
      
      This has the neat side-effect that we don't enable ports prematurely
      by restoring bogus state from the saved register values.
      Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      a261b246
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      drm/i915: read out the modeset hw state at load and resume time · 24929352
      Daniel Vetter 提交于
      ... instead of resetting a few things and hoping that this will work
      out.
      
      To properly disable the output pipelines at the initial modeset after
      resume or boot up we need to have an accurate picture of which outputs
      are enabled and connected to which crtcs. Otherwise we risk disabling
      things at the wrong time, which can lead to hangs (or at least royally
      confused panels), both requiring a walk to the reset button to fix.
      
      Hence read out the hw state with the freshly introduce get_hw_state
      functions and then sanitize it afterwards.
      
      For a full modeset readout (which would allow us to avoid the initial
      modeset at boot up) a few things are still missing:
      - Reading out the mode from the pipe, especially the dotclock
        computation is quite some fun.
      - Reading out the parameters for the stolen memory framebuffer and
        wrapping it up.
      - Reading out the pch pll connections - luckily the disable code
        simply bails out if the crtc doesn't have a pch pll attached (even
        for configurations that would need one).
      
      This patch here turned up tons of smelly stuff around resume: We
      restore tons of register in seemingly random way (well, not quite, but
      we're not too careful either), which leaves the hw in a rather
      ill-defined state: E.g. the port registers are sometimes
      unconditionally restore (lvds, crt), leaving us with an active
      encoder/connector but no active pipe connected to it. Luckily the hw
      state sanitizer detects this madness and fixes things up a bit.
      
      v2: When checking whether an encoder with active connectors has a crtc
      wire up to it, check for both the crtc _and_ it's active state.
      
      v3:
      - Extract intel_sanitize_encoder.
      - Manually disable active encoders without an active pipe.
      
      v4: Correclty fix up the pipe<->plane mapping on machines where we
      switch pipes/planes. Noticed by Chris Wilson, who also provided the
      fixup.
      
      v5: Spelling fix in a comment, noticed by Paulo Zanoni
      Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      24929352
  3. 23 8月, 2012 1 次提交
  4. 07 8月, 2012 1 次提交
  5. 26 7月, 2012 2 次提交
  6. 20 7月, 2012 1 次提交
  7. 05 7月, 2012 4 次提交
  8. 04 7月, 2012 3 次提交
  9. 26 6月, 2012 1 次提交
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      drm/i915: disable drm agp support for !gen3 with kms enabled · 01a06850
      Daniel Vetter 提交于
      This is the quick&dirty way Dave Airlie suggested to workaround the
      midlayer drm agp brain-damange. Note that i915_probe is only called
      when the driver has ksm enabled, so no need to check for that.
      
      We also need to move the intel_agp_enabled check at the right place.
      Note that the only thing this does is enforce the correct module load
      order (by using a symbol from intel-agp.ko) to ensure that the fake
      agp driver is ready before the drm core tries to set up the agp stuff.
      
      v2: Add a comment to explain why gen3 needs all this legacy fake agp
      stuff - we've shipped an XvMC library with a kms-enabled ddx that
      requires it (but only on gen3).
      
      v3: Make it clear that this is only a gen3 issue in the comment.
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NEugeni Dodonov <eugeni.dodonov@intel.com>
      Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      01a06850
  10. 21 6月, 2012 2 次提交
  11. 20 6月, 2012 1 次提交
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      drm/i915: don't call modeset_init_hw in i915_reset · 8e88a2bd
      Daniel Vetter 提交于
      It seems to blow up my ilk in all kinds of strange ways. And now that
      we're no longer resetting the entire modeset state, it shouldn't be
      necessary any longer.
      
      This essentially reverts
      
      commit f817586c
      Author: Daniel Vetter <daniel.vetter@ffwll.ch>
      Date:   Tue Apr 10 15:50:11 2012 +0200
      
          drm/i915: re-init modeset hw state after gpu reset
      
      safe for the introduction of modeset_init_hw, that one is nice to
      prevent code duplication between driver load and resume.
      
      v2: Add a comment to the code to warn future travellers of the dragon
      dungeon ahead, suggested by Chris Wilson.
      Acked-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      8e88a2bd
  12. 18 6月, 2012 1 次提交
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      drm/i915: fixup hangman rebase goof-up · e080b915
      Daniel Vetter 提交于
      I've added a bit of logic such that running the hangman test on chips
      without any hw reset support at all doesn't wedge the gpu because the
      reset failed. This relied on checking for non-null stop_rings.
      Unfortunately I've botched a rebase somewhere and stop_rings is still
      cleared at the old place before the reset code.
      
      Fix this up so that running the i-g-t tests on gen2/3 doesn't result
      in a wedged gpu.
      
      v2: Actually remove the lines instead of adding them twice ... my git
      license should be revoked immediately.
      Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      e080b915
  13. 14 6月, 2012 2 次提交
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      drm/i915: reset the GPU on context fini · 8e96d9c4
      Ben Widawsky 提交于
      It's the only way we know how to make the GPU actually forget about the
      default context.
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      8e96d9c4
    • B
      drm/i915: preliminary context support · 254f965c
      Ben Widawsky 提交于
      Very basic code for context setup/destruction in the driver.
      
      Adds the file i915_gem_context.c This file implements HW context
      support. On gen5+ a HW context consists of an opaque GPU object which is
      referenced at times of context saves and restores.  With RC6 enabled,
      the context is also referenced as the GPU enters and exists from RC6
      (GPU has it's own internal power context, except on gen5).  Though
      something like a context does exist for the media ring, the code only
      supports contexts for the render ring.
      
      In software, there is a distinction between contexts created by the
      user, and the default HW context. The default HW context is used by GPU
      clients that do not request setup of their own hardware context. The
      default context's state is never restored to help prevent programming
      errors. This would happen if a client ran and piggy-backed off another
      clients GPU state.  The default context only exists to give the GPU some
      offset to load as the current to invoke a save of the context we
      actually care about. In fact, the code could likely be constructed,
      albeit in a more complicated fashion, to never use the default context,
      though that limits the driver's ability to swap out, and/or destroy
      other contexts.
      
      All other contexts are created as a request by the GPU client. These
      contexts store GPU state, and thus allow GPU clients to not re-emit
      state (and potentially query certain state) at any time. The kernel
      driver makes certain that the appropriate commands are inserted.
      
      There are 4 entry points into the contexts, init, fini, open, close.
      The names are self-explanatory except that init can be called during
      reset, and also during pm thaw/resume. As we expect our context to be
      preserved across these events, we do not reinitialize in this case.
      
      As Adam Jackson pointed out, The cutoff of 1MB where a HW context is
      considered too big is arbitrary. The reason for this is even though
      context sizes are increasing with every generation, they have yet to
      eclipse even 32k. If we somehow read back way more than that, it
      probably means BIOS has done something strange, or we're running on a
      platform that wasn't designed for this.
      
      v2: rename load/unload to init/fini (daniel)
      remove ILK support for get_size() (indirectly daniel)
      add HAS_HW_CONTEXTS macro to clarify supported platforms (daniel)
      added comments (Ben)
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      254f965c
  14. 05 6月, 2012 1 次提交
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      drm/i915: hold forcewake around ring hw init · b7884eb4
      Daniel Vetter 提交于
      Empirical evidence suggests that we need to: On at least one ivb
      machine when running the hangman i-g-t test, the rings don't properly
      initialize properly - the RING_START registers seems to be stuck at
      all zeros.
      
      Holding forcewake around this register init sequences makes chip reset
      reliable again. Note that this is not the first such issue:
      
      commit f01db988
      Author: Sean Paul <seanpaul@chromium.org>
      Date:   Fri Mar 16 12:43:22 2012 -0400
      
          drm/i915: Add wait_for in init_ring_common
      
      added delay loops to make RING_START and RING_CTL initialization
      reliable on the blt ring at boot-up. So I guess it won't hurt if we do
      this unconditionally for all force_wake needing gpus.
      
      To avoid copy&pasting of the HAS_FORCE_WAKE check I've added a new
      intel_info bit for that.
      
      v2: Fixup missing commas in static struct and properly handling the
      error case in init_ring_common, both noticed by Jani Nikula.
      
      Cc: stable@vger.kernel.org
      Reported-and-tested-by: NYang Guang <guang.a.yang@intel.com>
      Reviewed-by: NEugeni Dodonov <eugeni.dodonov@intel.com>
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50522Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      b7884eb4
  15. 23 5月, 2012 1 次提交
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      i915: add dmabuf/prime buffer sharing support. · 1286ff73
      Daniel Vetter 提交于
      This adds handle->fd and fd->handle support to i915, this is to allow
      for offloading of rendering in one direction and outputs in the other.
      
      v2 from Daniel Vetter:
      - fixup conflicts with the prepare/finish gtt prep work.
      - implement ppgtt binding support.
      
      Note that we have squat i-g-t testcoverage for any of the lifetime and
      access rules dma_buf/prime support brings along. And there are quite a
      few intricate situations here.
      
      Also note that the integration with the existing code is a bit
      hackish, especially around get_gtt_pages and put_gtt_pages. It imo
      would be easier with the prep code from Chris Wilson's unbound series,
      but that is for 3.6.
      
      Also note that I didn't bother to put the new prepare/finish gtt hooks
      to good use by moving the dma_buf_map/unmap_attachment calls in there
      (like we've originally planned for).
      
      Last but not least this patch is only compile-tested, but I've changed
      very little compared to Dave Airlie's version. So there's a decent
      chance v2 on drm-next works as well as v1 on 3.4-rc.
      
      v3: Right when I've hit sent I've noticed that I've screwed up one
      obj->sg_list (for dmar support) and obj->sg_table (for prime support)
      disdinction. We should be able to merge these 2 paths, but that's
      material for another patch.
      
      v4: fix the error reporting bugs pointed out by ickle.
      
      v5: fix another error, and stop non-gtt mmaps on shared objects
      stop pread/pwrite on imported objects, add fake kmap
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      1286ff73
  16. 22 5月, 2012 1 次提交
  17. 20 5月, 2012 3 次提交
  18. 10 5月, 2012 1 次提交
    • D
      drm/i915: enable semaphores on gen6 if dmar is not active · 59de3295
      Daniel Vetter 提交于
      Inspired by the recent ppgtt regression report, where switching of
      dmar only for the gpu seems to fix things completely, I've looked
      again at the semaphores+vt-d situation.
      
      Contrary to my earlier testing a few months back my system is now
      stable with dmar disabled for the igd, and not only when disabling
      dmar completely.
      
      So I'm rather hopeful that all our recent fixes for snb have changed
      things for code and it's time to try enabling semaphores again. We've
      also had issues with enabling semaphores which are not vt-d related,
      but I guess these are all fixed by the autoreport-disabling and lazy
      request fix. And there's only one way to find out whether there are
      still other issues ...
      
      When I've tried to apply this patch I've noticed that semaphores on
      gen6 have already silently been enabled in
      
      commit 2911a35b
      Author: Ben Widawsky <ben@bwidawsk.net>
      Date:   Thu Apr 5 14:47:36 2012 -0700
      
          drm/i915: use semaphores for the display plane
      
      Fix this up by only checking whether dmar is enabled on the gfx (not
      on the entire system).
      Reviewed-by: NBen Widawsky <ben@bwidawsk.net>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      59de3295
  19. 06 5月, 2012 8 次提交
  20. 03 5月, 2012 2 次提交