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  1. 14 5月, 2009 1 次提交
  3. 30 3月, 2009 1 次提交
    • M
      MIPS: Alchemy: unify CPU model constants. · 270717a8
      由 Manuel Lauss 提交于 
      This patch removes the various CPU_AU1??? model constants in favor of
a single CPU_ALCHEMY one.

All currently existing Alchemy models are identical in terms of cpu
core and cache size/organization.  The parts of the mips kernel which
need to know the exact CPU revision extract it from the c0_prid register
already; and finally nothing else in-tree depends on those any more.

Should a new variant with slightly different "company options" and/or
"processor revision" bits in c0_prid appear, it will be supported
immediately (minus an exact model string in cpuinfo).
Signed-off-by: NManuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      270717a8
  5. 24 3月, 2009 1 次提交
  7. 31 1月, 2009 1 次提交
  9. 06 9月, 2008 1 次提交
  11. 26 6月, 2008 1 次提交
  13. 16 6月, 2008 2 次提交
  15. 29 4月, 2008 2 次提交
  17. 08 4月, 2008 1 次提交
  19. 12 3月, 2008 1 次提交
  21. 20 2月, 2008 1 次提交
    • R
      [MIPS] Handle I-cache coherency in flush_cache_range() · 2eaa7ec2
      由 Ralf Baechle 提交于 
      So far flush_cache_range() did't consider the I-cache largely because it
did rarely ever matter to real world code.  This was working primarily
because normally code and data are don't share the same pages - with the
exception of MIPS16 code which uses address constants embedded between
the code.   The following sequence of events may break the code:

 o MIPS16 executable being loaded
 o dynamic linker relocates the address constants embedded into the code:
 o   Uses mprotect(2) to make code pages PROT_READ|PROT_WRITE
 o   Performs the actual relocations by writing to the pages which likely
     are COW.  Because no PROT_EXEC is set I-cache coherence will not be
     considered.
 o   Uses mprotect(2) to switch code pages back to PROT_READ|PROT_EXEC.
     This results in a call to flush_cache_range() which also does not
     consider I-caches.
 o => executing the page just having been relocated may now result in the
   I-cache getting refilled with stale data from memory.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      2eaa7ec2
  23. 03 2月, 2008 1 次提交
  25. 29 1月, 2008 4 次提交
  27. 16 11月, 2007 1 次提交
    • R
      [MIPS] Sibyte: resurrect old cache hack. · a754f708
      由 Ralf Baechle 提交于 
      The recent switch of the Sibyte SOCs from the processor specific cache
managment code in c-sb1.c to c-r4k.c lost this old hack

    [MIPS] Hack for SB1 cache issues

    Removing flush_icache_page a while ago broke SB1 which was using an empty
    flush_data_cache_page function.  This glues things well enough so a more
    efficient but also more intrusive solution can be found later.
Signed-Off-By: NThiemo Seufer <ths@networkno.de>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

in the hope it was no longer needed.  As it turns it still is so resurrect
it until there is a better solution.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      a754f708
  29. 30 10月, 2007 1 次提交
    • R
      [MIPS] MT: Fix bug in multithreaded kernels. · a76ab5c1
      由 Ralf Baechle 提交于 
      When GDB writes a breakpoint into address area of inferior process the
kernel needs to invalidate the modified memory in the inferior which
is done by calling flush_cache_page which in turns calls
r4k_flush_cache_page and local_r4k_flush_cache_page for VSMP or SMTC
kernel via r4k_on_each_cpu().

As the VSMP and SMTC SMP kernels for 34K are running on a single shared
caches it is possible to get away without interprocessor function calls.
This optimization is implemented in r4k_on_each_cpu, so
local_r4k_flush_cache_page is only ever called on the local CPU.

This is where the following code in local_r4k_flush_cache_page() strikes:

        /*
         * If ownes no valid ASID yet, cannot possibly have gotten
         * this page into the cache.
         */
        if (cpu_context(smp_processor_id(), mm) == 0)
                return;

On VSMP and SMTC had a function of cpu_context() for each CPU(TC).

So in case another CPU than the CPU executing local_r4k_cache_flush_page
has not accessed the mm but one of the other CPUs has there may be data
to be flushed in the cache yet local_r4k_cache_flush_page will falsely
return leaving the I-cache inconsistent for the breakpoint.

While the issue was discovered with GDB it also exists in
local_r4k_flush_cache_range() and local_r4k_flush_cache().

Fixed by introducing a new function has_valid_asid which on MT kernels
returns true if a mm is active on any processor in the system.

This is relativly expensive since for memory acccesses in that loop
cache misses have to be assumed but it seems the most viable solution
for 2.6.23 and older -stable kernels.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      a76ab5c1
  31. 17 10月, 2007 1 次提交
  33. 12 10月, 2007 4 次提交
  35. 01 8月, 2007 1 次提交
  37. 11 7月, 2007 1 次提交
  39. 30 11月, 2006 2 次提交
  41. 02 10月, 2006 1 次提交
  43. 27 9月, 2006 4 次提交
    • R
      [MIPS] c-r4k: Convert init functions from inline to __init. · a00f6310
      由 Ralf Baechle 提交于 
      With more recent compilers inline doesn't necessarily means a function
will always be inlined.  So leave that decission to the compiler and
make the function as __init.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      a00f6310
    • A
      [MIPS] Do not use drop_mmu_context to flusing other task's VIPT I-cache. · f6502791
      由 Atsushi Nemoto 提交于 
      c-r4k.c and c-sb1.c use drop_mmu_context() to flush virtually tagged
I-caches, but this does not work for flushing other task's icache.  This
is for example triggered by copy_to_user_page() called from ptrace(2).
Use indexed flush for such cases.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      f6502791
    • R
      [MIPS] Retire flush_icache_page from mm use. · 585fa724
      由 Ralf Baechle 提交于 
      On the 34K the redundant cache operations were causing excessive stalls
resulting in realtime code running on the second VPE missing its deadline.
For all other platforms this patch is just a significant performance
improvment as illustrated by below benchmark numbers.

Processor, Processes - times in microseconds - smaller is better
------------------------------------------------------------------------------
Host                 OS  Mhz null null      open slct sig  sig  fork exec sh
                             call  I/O stat clos TCP  inst hndl proc proc proc
--------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
25Kf      2.6.18-rc4     533 0.49 1.16 7.57 33.4 30.5 1.34 12.4 5497 17.K 54.K
25Kf      2.6.18-rc4-p   533 0.49 1.16 6.68 23.0 30.7 1.36 8.55 5030 16.K 48.K
4Kc       2.6.18-rc4      80 4.21 15.0 131. 289. 261. 16.5 258. 18.K 70.K 227K
4Kc       2.6.18-rc4-p    80 4.34 13.1 128. 285. 262. 18.2 258. 12.K 52.K 176K
34Kc      2.6.18-rc4      40 5.01 14.0 61.6 90.0 477. 17.9 94.7 29.K 108K 342K
34Kc      2.6.18-rc4-p    40 4.98 13.9 61.2 89.7 475. 17.6 93.7 8758 44.K 158K
BCM1480   2.6.18-rc4     700 0.28 0.60 3.68 5.92 16.0 0.78 5.08 931. 3163 15.K
BCM1480   2.6.18-rc4-p   700 0.28 0.61 3.65 5.85 16.0 0.79 5.20 395. 1464 8385
TX49-16K  2.6.18-rc3     197 0.73 2.41 19.0 37.8 82.9 2.94 17.5 4438 14.K 56.K
TX49-16K  2.6.18-rc3-p   197 0.73 2.40 19.9 36.3 82.9 2.94 23.4 2577 9103 38.K
TX49-32K  2.6.18-rc3     396 0.36 1.19 6.80 11.8 41.0 1.46 8.17 2738 8465 32.K
TX49-32K  2.6.18-rc3-p   396 0.36 1.19 6.82 10.2 41.0 1.46 8.18 1330 4638 18.K
    
Original patch by me with enhancements by Atsushi Nemoto.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
      585fa724
    • R
      [MIPS] c-r4k: Typo fix. · df586d59
      由 Ralf Baechle 提交于 
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      df586d59
  45. 14 7月, 2006 4 次提交
  47. 01 7月, 2006 1 次提交
  49. 30 6月, 2006 1 次提交