Add and initialize the gpio_wp and gpio_cd members.  We need to
ensure that all users are covered, because GPIO 0 may be valid.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Acked-by: NLinus Walleij <linus.walleij@stericsson.com>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This reverts commit 9e9f46c4.

Quoting from the commit message:

 "At this point, it seems to solve more problems than it causes, so let's
  try using it by default.  It's an easy revert if it ends up causing
  trouble."

And guess what? The _CRS code causes trouble.
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Thanks to Cavium Inc. for the code contribution and help.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The SMP implementation of suspend and hibernate depends on CPU hotplugging.
In the past we didn't have CPU hotplug so suspend and hibernation were not
possible on SMP systems.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Each platform has to add support for CPU hotplugging itself by providing
suitable definitions for the cpu_disable and cpu_die of the smp_ops
methods and setting SYS_SUPPORTS_HOTPLUG_CPU.  A platform should only set
SYS_SUPPORTS_HOTPLUG_CPU once all it's smp_ops definitions have the
necessary changes.  This patch contains the changes to the dummy smp_ops
definition for uni-processor systems.

Parts of the code contributed by Cavium Inc.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This fixes kernel.org bugzilla 13596, see
http://bugzilla.kernel.org/show_bug.cgi?id=13596

Reported-by: dvice_null@yahoo.com
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This fixes kernel.org bugzilla 13595, see
http://bugzilla.kernel.org/show_bug.cgi?id=13595

Reported-by: dvice_null@yahoo.com
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

We can't perform any flushes on SMP from swsusp_arch_resume because
interrupts are disabled.  A cross-CPU flush is unnecessary anyway
because all but the local CPU have already been disabled.  A local
flush is not needed either because we didn't change any mappings.  So
just delete the code.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Some of the were relying into smp.h being dragged in by another header
which of course is fragile.  <asm/cpu-info.h> uses smp_processor_id()
only in macros and including smp.h there leads to an include loop, so
don't change cpu-info.h.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

In the past this file somehow used to be dragged in.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

To support domain-isolation usages, the platform hardware must be
capable of uniquely identifying the requestor (source-id) for each
interrupt message. Without source-id checking for interrupt remapping
, a rouge guest/VM with assigned devices can launch interrupt attacks
to bring down anothe guest/VM or the VMM itself.

This patch adds source-id checking for interrupt remapping, and then
really isolates interrupts for guests/VMs with assigned devices.

Because PCI subsystem is not initialized yet when set up IOAPIC
entries, use read_pci_config_byte to access PCI config space directly.
Signed-off-by: NWeidong Han <weidong.han@intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Fix the incorrect "select" directives by dropping the "CONFIG_"
prefixes, and correcting the typo "H8S2768" to "H8S2678".
Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca>
Acked-by: NYoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

That's HAVE_PERF_COUNTERS not HAVE_PERF_COUNTER. This was right
initially but I seem to have screwed it up while re-typing it out
by hand on another machine when I checked it in. Hmph.
Reported-by: NRobert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

commit dbe6f186
("dma-mapping: mark dma_sync_single and dma_sync_sg as deprecated"
conveniently broke every single SH build.

In the future it would be great if people could at least bother
figuring out how to use grep.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

SH7786 is roughly identical to SH-X3 proto SMP, though there are only 2
CPUs. This just wraps in to the existing SH-X3 SMP code with some minor
changes for SH7786, including wiring up the IPIs properly, enabling
IRQ_PER_CPU, and so forth.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Now that sh64 also can use the uncached section, wire up the fixmap for
it as well.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

set_pte_phys() presently uses the global flush_tlb_one(), which locks on
SMP trying to do the IPI. As we have not even initialized the other CPUs
at this point, switch to the local_ variant so the flush happens on the
boot CPU.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Crib the x86 cpu_idle_wait() implementation and shove it in with the
idle code, subsequently enabling ARCH_HAS_CPU_IDLE_WAIT.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Since dmanr is unsigned, negatives are wrapped and caught by the other test.
Signed-off-by: NRoel Kluin <roel.kluin@gmail.com>
Acked-by: NJesper Nilsson <jesper.nilsson@axis.com>

The recent deprecation of dma_sync_{sg,single} ironically broke Blackfin
systems.  This is because we don't define dma_sync_sg_for_cpu at all, so
until the DMA asm-generic conversion/cleanup is done after the next
release, simply stub out the dma_sync_sg_for_{cpu,device} functions.
Signed-off-by: NFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

We don't support the BF535 at all, and the exception 0x2A text specific to
it is pretty verbose and confusing (since the behavior is simply odd), so
punt it to keep the noise down.
Signed-off-by: NYi Li <yi.li@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Make sure we process the kernel command line before poking the hardware,
so that we can process early printk.  This helps ensure that if you boot
a kernel configured for a different processor, something will be left in
the log buffer.
Signed-off-by: NRobin Getz <robin.getz@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The GPTMR0_CLOCKSOURCE Kconfig option requires the gptimers framework, so
make sure it is selected when this option is enabled.
Reported-by: NPeter Meerwald <pmeerw@pmeerw.net>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The port1 disable stuff was dropped from the USB ISP1760, so update the
Blackfin boards accordingly.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The BF526-EZBRD changed SDRAM chips between board revisions, so create a
timing table that can accommodate both.
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

We defined SDRAM_tRAS to TRAS_4, but then wrongly defined SDRAM_tRAS_num
to 3.
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Many aspects of the Blackfin memory map is exactly the same across all
variants.  Rather than copy and paste all of these duplicated values in
each header, unify all of these into the common Blackfin memory map header
file.  In the process, push down BF561 SMP specific stuff to the BF561
specific header to keep the noise down.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Rather than use "Linux" in the boot image name (as this is redundant --
the image type is already set to "linux"), use the CPU name.  This makes
it fairly obvious when a wrong image is accidentally booted.  Otherwise
there is no kernel output and you waste time scratching your head
wondering wtf just happened.
Signed-off-by: NRobin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The current cache options don't really represent the hardware features.
They end up setting different aspects of the hardware so that the end
result is to turn on/off the cache.  Unfortunately, when we hit cache
problems with the hardware, it's difficult to test different settings to
root cause the problem.  The current settings also don't cleanly allow for
different caching behaviors with different regions of memory.

So split the configure options such that they properly reflect the settings
that are applied to the hardware.
Signed-off-by: NJie Zhang <jie.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NPhilippe Gerum <rpm@xenomai.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NPhilippe Gerum <rpm@xenomai.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NPhilippe Gerum <rpm@xenomai.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NPhilippe Gerum <rpm@xenomai.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Now that 0.1 of the BF51x is coming out, allow people to build for it.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The BF526-EZBRD has a SST SPI flash on it, not a ST Micro.
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

We read the SWRST (Software Reset) register to get at the last reset
state, and then we may configure the DOUBLE_FAULT bit to control behavior
when a double fault occurs.  But if the lower bits of the register is
already set (like UART boot mode on a BF54x), we inadvertently make the
system reset by writing to the SYSTEM_RESET field at the same time.  So
make sure the lower 4 bits are always cleared.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>