1. 04 1月, 2013 1 次提交
    • G
      SPARC: drivers: remove __dev* attributes. · 7c9503b8
      Greg Kroah-Hartman 提交于
      CONFIG_HOTPLUG is going away as an option.  As a result, the __dev*
      markings need to be removed.
      
      This change removes the use of __devinit, __devexit_p, __devinitdata,
      and __devexit from these drivers.
      
      Based on patches originally written by Bill Pemberton, but redone by me
      in order to handle some of the coding style issues better, by hand.
      
      Cc: Bill Pemberton <wfp5p@virginia.edu>
      Cc: "David S. Miller" <davem@davemloft.net>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      7c9503b8
  2. 12 12月, 2012 1 次提交
  3. 17 10月, 2012 1 次提交
  4. 15 10月, 2012 1 次提交
  5. 11 10月, 2012 1 次提交
    • D
      sparc64: Fix deficiencies in sun4v error reporting. · f88620b9
      David S. Miller 提交于
      Missing error types, attributes, and report fields.  Pad out
      to 64-bytes.
      
      Make string reporting cleaner and easier to extend in the future using
      "const char *" arrays that index by either bit position, or absolute
      field value.
      
      Report the raw 64-byte error report as a sequence of u64s before the
      annotated version.
      
      Only report fields which are valid, given the context and the
      attribute bits which are set.
      
      For shutdown requests, use the local copy of the error report not the
      one we just freed up back to the queue.  Also, use orderly_poweroff()
      just like the Domain Services shutdown request code does.
      
      If the real-address reported is "-1" (unknown) try to disassemble the
      instruction to report the effective address of the access.  Only do
      this in privileged mode.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      f88620b9
  6. 09 10月, 2012 4 次提交
    • D
      sparc64: Support transparent huge pages. · 9e695d2e
      David Miller 提交于
      This is relatively easy since PMD's now cover exactly 4MB of memory.
      
      Our PMD entries are 32-bits each, so we use a special encoding.  The
      lowest bit, PMD_ISHUGE, determines the interpretation.  This is possible
      because sparc64's page tables are purely software entities so we can use
      whatever encoding scheme we want.  We just have to make the TLB miss
      assembler page table walkers aware of the layout.
      
      set_pmd_at() works much like set_pte_at() but it has to operate in two
      page from a table of non-huge PTEs, so we have to queue up TLB flushes
      based upon what mappings are valid in the PTE table.  In the second regime
      we are going from huge-page to non-huge-page, and in that case we need
      only queue up a single TLB flush to push out the huge page mapping.
      
      We still have 5 bits remaining in the huge PMD encoding so we can very
      likely support any new pieces of THP state tracking that might get added
      in the future.
      
      With lots of help from Johannes Weiner.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      Cc: Andrea Arcangeli <aarcange@redhat.com>
      Cc: Johannes Weiner <hannes@cmpxchg.org>
      Cc: Gerald Schaefer <gerald.schaefer@de.ibm.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      9e695d2e
    • D
      sparc64: Eliminate PTE table memory wastage. · c460bec7
      David Miller 提交于
      We've split up the PTE tables so that they take up half a page instead of
      a full page.  This is in order to facilitate transparent huge page
      support, which works much better if our PMDs cover 4MB instead of 8MB.
      
      What we do is have a one-behind cache for PTE table allocations in the
      mm struct.
      
      This logic triggers only on allocations.  For example, we don't try to
      keep track of free'd up page table blocks in the style that the s390 port
      does.
      
      There were only two slightly annoying aspects to this change:
      
      1) Changing pgtable_t to be a "pte_t *".  There's all of this special
         logic in the TLB free paths that needed adjustments, as did the
         PMD populate interfaces.
      
      2) init_new_context() needs to zap the pointer, since the mm struct
         just gets copied from the parent on fork.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      Cc: Andrea Arcangeli <aarcange@redhat.com>
      Cc: Johannes Weiner <hannes@cmpxchg.org>
      Cc: Gerald Schaefer <gerald.schaefer@de.ibm.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      c460bec7
    • D
      sparc64: Only support 4MB huge pages and 8KB base pages. · 15b9350a
      David Miller 提交于
      Narrowing the scope of the page size configurations will make the
      transparent hugepage changes much simpler.
      
      In the end what we really want to do is have the kernel support multiple
      huge page sizes and use whatever is appropriate as the context dictactes.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      Cc: Andrea Arcangeli <aarcange@redhat.com>
      Cc: Johannes Weiner <hannes@cmpxchg.org>
      Cc: Gerald Schaefer <gerald.schaefer@de.ibm.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      15b9350a
    • S
      readahead: fault retry breaks mmap file read random detection · 45cac65b
      Shaohua Li 提交于
      .fault now can retry.  The retry can break state machine of .fault.  In
      filemap_fault, if page is miss, ra->mmap_miss is increased.  In the second
      try, since the page is in page cache now, ra->mmap_miss is decreased.  And
      these are done in one fault, so we can't detect random mmap file access.
      
      Add a new flag to indicate .fault is tried once.  In the second try, skip
      ra->mmap_miss decreasing.  The filemap_fault state machine is ok with it.
      
      I only tested x86, didn't test other archs, but looks the change for other
      archs is obvious, but who knows :)
      Signed-off-by: NShaohua Li <shaohua.li@fusionio.com>
      Cc: Rik van Riel <riel@redhat.com>
      Cc: Wu Fengguang <fengguang.wu@intel.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      45cac65b
  7. 03 10月, 2012 1 次提交
  8. 07 9月, 2012 3 次提交
    • D
      sparc64: Use cpu_pgsz_mask for linear kernel mapping config. · c69ad0a3
      David S. Miller 提交于
      This required a little bit of reordering of how we set up the memory
      management early on.
      
      We now only know the final values of kern_linear_pte_xor[] after we
      take over the trap table and start processing TLB misses ourselves.
      
      So once we fill those values in we re-clear the kernel's 4M TSB and
      flush the TLBs.  That way if we find we support larger than 4M pages
      we won't have any stale smaller page size entries in the TSB.
      
      SUN4U Panther support for larger page sizes should now be extremely
      trivial but I have no hardware on which to test it and I believe
      that some of the sun4u TLB miss assembler needs to be audited first
      to make sure it really can handle larger than 4M PTEs properly.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c69ad0a3
    • D
      sparc64: Probe cpu page size support more portably. · ce33fdc5
      David S. Miller 提交于
      On sun4v, interrogate the machine description.  This code is extremely
      defensive in nature, and a lot of the checks can probably be removed.
      
      On sun4u things are a lot simpler.  There are the page sizes all chips
      support, and then Panther adds 32MB and 256MB pages.
      
      Report the probed value in /proc/cpuinfo
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ce33fdc5
    • D
      sparc64: Support 2GB and 16GB page sizes for kernel linear mappings. · 4f93d21d
      David S. Miller 提交于
      SPARC-T4 supports 2GB pages.
      
      So convert kpte_linear_bitmap into an array of 2-bit values which
      index into kern_linear_pte_xor.
      
      Now kern_linear_pte_xor is used for 4 page size aligned regions,
      4MB, 256MB, 2GB, and 16GB respectively.
      
      Enabling 2GB pages is currently hardcoded using a check against
      sun4v_chip_type.  In the future this will be done more cleanly
      by interrogating the machine description which is the correct
      way to determine this kind of thing.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      4f93d21d
  9. 15 8月, 2012 1 次提交
    • D
      sparc64: Be less verbose during vmemmap population. · 2856cc2e
      David S. Miller 提交于
      On a 2-node machine with 256GB of ram we get 512 lines of
      console output, which is just too much.
      
      This mimicks Yinghai Lu's x86 commit c2b91e2e
      (x86_64/mm: check and print vmemmap allocation continuous) except that
      we aren't ever going to get contiguous block pointers in between calls
      so just print when the virtual address or node changes.
      
      This decreases the output by an order of 16.
      
      Also demote this to KERN_DEBUG.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      2856cc2e
  10. 27 7月, 2012 15 次提交
  11. 28 5月, 2012 3 次提交
  12. 23 5月, 2012 1 次提交
  13. 20 5月, 2012 3 次提交
  14. 16 5月, 2012 2 次提交
  15. 15 5月, 2012 1 次提交
  16. 14 5月, 2012 1 次提交
    • D
      sparc32: Move cache and TLB flushes over to method ops. · 5d83d666
      David S. Miller 提交于
      This eliminated most of the remaining users of btfixup.
      
      There are some complications because of the special cases we
      have for sun4d, leon, and some flavors of viking.
      
      It was found that there are no cases where a flush_page_for_dma
      method was not hooked up to something, so the "noflush" iommu
      methods were removed.
      
      Add some documentation to the viking_sun4d_smp_ops to describe exactly
      the hardware bug which causes us to need special TLB flushing on
      sun4d.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5d83d666