1. 07 12月, 2016 4 次提交
  2. 06 12月, 2016 8 次提交
  3. 04 12月, 2016 1 次提交
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  5. 30 11月, 2016 2 次提交
  6. 28 11月, 2016 1 次提交
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  10. 17 11月, 2016 6 次提交
  11. 16 11月, 2016 4 次提交
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  14. 10 11月, 2016 2 次提交
  15. 08 11月, 2016 2 次提交
  16. 01 11月, 2016 1 次提交
    • A
      bgmac: stop clearing DMA receive control register right after it is set · fcdefcca
      Andy Gospodarek 提交于
      Current bgmac code initializes some DMA settings in the receive control
      register for some hardware and then immediately clears those settings.
      Not clearing those settings results in ~420Mbps *improvement* in
      throughput; this system can now receive frames at line-rate on Broadcom
      5871x hardware compared to ~520Mbps today.  I also tested a few other
      values but found there to be no discernible difference in CPU
      utilization even if burst size and prefetching values are different.
      
      On the hardware tested there was no need to keep the code that cleared
      all but bits 16-17, but since there is a wide variety of hardware that
      used this driver (I did not look at all hardware docs for hardware using
      this IP block), I find it wise to move this call up and clear bits just
      after reading the default value from the hardware rather than completely
      removing it.
      
      This is a good candidate for -stable >=3.14 since that is when the code
      that was supposed to improve performance (but did not) was introduced.
      Signed-off-by: NAndy Gospodarek <gospo@broadcom.com>
      Fixes: 56ceecde ("bgmac: initialize the DMA controller of core...")
      Cc: Hauke Mehrtens <hauke@hauke-m.de>
      Acked-by: NHauke Mehrtens <hauke@hauke-m.de>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      fcdefcca
  17. 28 10月, 2016 1 次提交