Merge branch 'next/devel-samsung-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc

From Kukjin Kim:

This is including Samsung small updates(developments) for v3.8.

Add node PL330 MDMA1 and UART3 for DEBUG_LL and secondary cpu bring-up
for exynos4412.

* 'next/devel-samsung-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: dts: add node for PL330 MDMA1 controller for exynos4
  ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412
  ARM: EXYNOS: add UART3 to DEBUG_LL ports
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge branch 'next/pinctrl-samsung-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc

From Kukjin Kim:
* 'next/pinctrl-samsung-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  pinctrl: samsung: Do not initialise statics to 0
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge branch 'next/cam-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc

From Kukjin Kim:
Just adding camif gpio setup and clkdev.

* 'next/cam-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: S3C24XX: Add clkdev entry for camif-upll clock
  ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers
  + Linux 3.7-rc6

Conflicts due to the 3.7-rc6 sync: arch/arm/mach-highbank/system.c
include/linux/clk-provider.h, resolved as in other branches.
Signed-off-by: NOlof Johansson <olof@lixom.net>

The recent commit "ARM: EXYNOS: add support for EXYNOS5440 SoC" broke
support for exynos5250 because of_machine_is_compatible() was used too
early in the boot process.  It also probably meant that the exynos5440
failed to use the proper iotable.  Switch to use
of_flat_dt_is_compatible() in both of these cases.

The failure I was seeing in exynos5250 because of this was:
  Division by zero in kernel.
  [<80015ed4>] (unwind_backtrace+0x0/0xec) from [<8045c7a4>] (dump_stack+0x20/0x24)
  [<8045c7a4>] (dump_stack+0x20/0x24) from [<80012990>] (__div0+0x20/0x28)
  [<80012990>] (__div0+0x20/0x28) from [<8021ab04>] (Ldiv0_64+0x8/0x18)
  [<8021ab04>] (Ldiv0_64+0x8/0x18) from [<80068560>] (__clocksource_updatefreq_scale+0x54/0x134)
  [<80068560>] (__clocksource_updatefreq_scale+0x54/0x134) from [<8006865c>] (__clocksource_register_scale+0x1c/0x54)
  [<8006865c>] (__clocksource_register_scale+0x1c/0x54) from [<80612a18>] (exynos_timer_init+0x100/0x1e8)
  [<80612a18>] (exynos_timer_init+0x100/0x1e8) from [<8060d184>] (time_init+0x28/0x38)
  [<8060d184>] (time_init+0x28/0x38) from [<8060a754>] (start_kernel+0x1e0/0x3c8)
  [<8060a754>] (start_kernel+0x1e0/0x3c8) from [<40008078>] (0x40008078)
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
[olofj: fixed two build errors, one missing include and one !CONFIG_OF failure]
Signed-off-by: NOlof Johansson <olof@lixom.net>

Add missing PL330 MDMA1 controller node to the device tree (DT).

[ Currently there is no problem with using 'non-secure' mdma1 address
  instead of 'secure' one on revision 0 of Exynos4210 SOC (as used by
  Universal C210 board) as this SOC revision is unsupported by DT. ]
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Exynos4412 uses different information register for each core. This
patch adjusts the bring-up code to take that into account.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Reviewed-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add support for using UART3 for DEBUG_LL on exynos.

[dianders: added depend on ARCH_EXYNOS.]
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The s3c-camif driver uses "camera" clock conn_id for the "camif-upll"
(s3c244x) and "camera" (s3c64xx) platform clock. By adding this new
clkdev entry the platform differences are isolated from the driver.
Signed-off-by: NSylwester Nawrocki <sylvester.nawrocki@gmail.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds default helper functions for the camera port
pin configuration. Whenever pinctrl support for s3c24xx/s3c64xx
SoCs is available these code should be removed and proper pinctrl
API should be used in the CAMIF driver.
Signed-off-by: NSylwester Nawrocki <sylvester.nawrocki@gmail.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Patch f055f1f6 [ARM: sunxi: Add sun4i and cubieboard support] missed
this sun4i.dtsi include file. This patch finally brings it upstream
enabling support for sun4i boards.
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>

Merge branch 'next/soc-exynos5440' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc

From Kukjin Kim:
This is adding support for exynos5440, including Quad ARM Cortex-A15
cores and its reference board SSDK5440.

Note, at this moment, just enabled minimal system part for initial kernel
boot and pinctrl driver.

* 'next/soc-exynos5440' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: dts: Add pin controller node for Samsung EXYNOS5440 SoC
  pinctrl: exynos5440: add pinctrl driver for Samsung EXYNOS5440 SoC
  ARM: dts: add initial dts file for EXYNOS5440, SSDK5440
  ARM: EXYNOS: add support for EXYNOS5440 SoC

Add/add conflict in arch/arm/boot/dts/Makefile.
Signed-off-by: NOlof Johansson <olof@lixom.net>

From Sascha Hauer:
ARM i.MX SoC updates for v3.8

* tag 'imx-soc-1' of git://git.pengutronix.de/git/imx/linux-2.6:
  ARM i.MX6: remove gate_mask from pllv3
  ARM i.MX6: Fix ethernet PLL clocks
  ARM i.MX6: rename PLLs according to datasheet
  ARM i.MX6: Add pwm support
  ARM i.MX51: Add pwm support
  ARM i.MX53: Add pwm support
  ARM: mx5: Replace clk_register_clkdev with clock DT lookup
Signed-off-by: NOlof Johansson <olof@lixom.net>

Static variables are initialised to 0 by GCC.
Fixes the following checkpatch error:
ERROR: do not initialise statics to 0 or NULL
FILE: pinctrl/pinctrl-samsung.c:50:
static unsigned int pin_base = 0;
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Pulling in a newer version of the depend branch from the gpio tree,
since there was some randconfig breakage introduced at the version we
had, and we want to keep those things as bisectable as possible. It's
not bad enough to warrant a rebase though, so there'll be a window of
exposure to this.

* depends/gpio-devel:
  gpio: SPEAr: add spi chipselect control driver
  gpio: gpio-max710x: Support device tree probing
  gpio: twl4030: Use only TWL4030_MODULE_LED for LED configuration
  gpio: tegra: read output value when gpio is set in direction_out
  gpio: pca953x: Add compatible strings to gpio-pca953x driver
  gpio: pca953x: Register an IRQ domain
  gpio: mvebu: Set free callback for gpio_chip
  gpio: tegra: Drop exporting static functions
  gpio: tegra: Staticize non-exported symbols
  gpio: tegra: fix suspend/resume apis
  gpio-pch: Set parent dev for gpio chip
  gpio: em: Fix build errors
Signed-off-by: NOlof Johansson <olof@lixom.net>

Now that the additional enable bits in the enet PLL are handled
as gates, the gate_mask is identical for all plls. Remove the
gate_mask from the code and use the BM_PLL_ENABLE bit for
enabling/disabling the PLL.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>

In current code the ethernet PLL is not handled correctly. The PLL runs at 500MHz
and has different outputs. Only the enet reference clock is implemented. This
patch changes the PLL so that it outputs 500MHz and adds the additional outputs
as dividers. This now matches the datasheet which says:

> This PLL synthesizes a low jitter clock from 24 MHz reference clock.
> The PLL outputs a 500 MHz clock. The reference clocks generated by this PLL are:
>  • Ref_PCIe = 125 MHz
>  • Ref_SATA = 100 MHz
>  • Ref_ethernet, which is configurable based on the PLL_ENET[1:0] register field.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>

In recent reference manuals the PLLs were renumbered. PLL8 now is
PLL6 and vice versa. Change the code according to the reference
manual to avoid confusion.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>

Similarly as it was done for mx6q, use a DT lookup in order to make maintainance
task for the clock devices easier.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add a new pinctrl driver for Samsung EXYNOS5440 SoC. The pin controller
module in EXYNOS5440 is different from the pin controller found on other
Samsung SoC. Hence, the pin controller driver for EXYNOS5440 SoC is
independent of the Samsung pinctrl framework.
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds initial dts file for EXYNOS5440 SoC and adds the
dts file for SSDK5440 board which is a kind of reference board.
More properties will be added later.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds support for EXYNOS5440 SoC which is including
ARM Cortex-A15 Quad cores.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

From Maxime Ripard:

Here is a pull request to add the support for Allwinner A10 SoCs.

* sunxi/soc2:
  ARM: sunxi: Add sunxi restart function via onchip watchdog
  ARM: sunxi: Add sun4i and cubieboard support
  ARM: sunxi: Add earlyprintk support for UART0 (sun4i)
  ARM: sunxi: Restructure sunxi dts/dtsi files
Signed-off-by: NOlof Johansson <olof@lixom.net>

From Kukjin Kim:
Here is Samsung DT for v3.8 and this is including DT for EXYNOS4X12
SoC, SMDK4412 board, pinctrl for exynos4x12, TMU, MFC, SATA and SATA
PHY.

As I commented on [4/7], this branch merged pinctrl/samsung to support
pinctrl for exynos4x12 without useless merge conflicts.

* samsung/pinctrl:
  pinctrl: samsung: Update error check for unsigned variables
  pinctrl: samsung: Add support for EXYNOS4X12
  Documentation: Update samsung-pinctrl device tree bindings documentation
  pinctrl: samsung: Add GPIO to IRQ translation
  pinctrl: exynos: Set pin function to EINT in irq_set_type of wake-up EINT
  pinctrl: samsung: Use per-bank IRQ domain for wake-up interrupts
  pinctrl: samsung: Use one GPIO chip per pin bank
  pinctrl: exynos: Use one IRQ domain per pin bank
  pinctrl: samsung: Include bank-specific eint offset in bank struct
  pinctrl: samsung: Hold pointer to driver data in bank struct
  pinctrl: samsung: Match pin banks with their device nodes
  ARM: dts: exynos4210-pinctrl: Add nodes for pin banks
  pinctrl: samsung: Distinguish between pin group and bank nodes
  pinctrl: samsung: Remove static pin enumerations
  pinctrl: samsung: Assing pin numbers dynamically
  pinctrl: samsung: Do not pass gpio_chip to pin_to_reg_bank
  pinctrl: samsung: Detect and handle unsupported configuration types

From Alexander Shiyan:

The main direction of this patchset - approaching the platform to the
possibility of using configurations with multiple platforms in a single
kernel. Added support of the majority of the necessary kernel symbol.
Also part of the driver code used only for the platform was moved to the
board code and converted to the use of standard drivers.

* clps711x/soc2:
  MAINTAINERS: Add ARM CLPS711X entry
  ARM: clps711x: Update defconfig due latest changes and new kernel symbols
  ARM: clps711x: Rename board files to match functionality
  ARM: clps711x: edb7211: Add support for NOR-Flash
  ARM: clps711x: Moving backlight controls of framebuffer driver to the board
  ARM: clps711x: p720t: Special driver for handling NAND memory is removed
  ARM: clps711x: Moving power management of framebuffer driver to the board
  ARM: clps711x: autcpu12: Special driver for handling NAND memory is removed
  ARM: clps711x: Unused empty "ACK" calls for IRQ-chips removed
  ARM: clps711x: Add FIQ interrupt handling
  ARM: clps711x: Implement usage "MULTI_IRQ_HANDLER" kernel option for a platform
  ARM: clps711x: Implement usage "SPARSE_IRQ" kernel option for a platform
  ARM: clps711x: cdb89712: Special driver for handling memory is removed
  ARM: clps711x: Always select AUTO_ZRELADDR for a platform
  ARM: clps711x: p720t: Unneeded inclusion of head-sa1100.S removed
  ARM: clps711x: Transform clps711x-framebuffer to platform driver and use it
  ARM: clps711x: p720t: Using "leds-gpio" driver for LED control
  ARM: clps711x: Using platform_driver for ethernet device

Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch moves the backlight controls for clps711x-framebuffer driver
to the board code. To control we use "generic-bl" driver.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
[olof: fixed space/tab whitespace in drivers/video/clps711xfb.c]
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch provide migration to using "gpio-nand" driver instead of using
special driver for handling NAND memory.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch moves the power management for clps711x-framebuffer driver
to the board code. To control we use "platform-lcd" driver.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch provide migration to using "gpio-nand" and "basic-mmio-gpio"
drivers instead of using special driver for handling NAND memory.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NOlof Johansson <olof@lixom.net>

CLPS711X-target CPU can have a several FIQ interrupts. With this patch
we adds handling for a one which will be used for ALSA PCM later.
Since FIQ have a separate handler we only add "mask" and "unmask" calls
which will used for enable/disable_irq functions.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NOlof Johansson <olof@lixom.net>