Since 93abe8e4 (clk: add non CONFIG_HAVE_CLK routines) code using clk.h
like this platform driver needs not depend on HAVE_CLK.
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Signed-off-by: NMark Brown <broonie@linaro.org>

On ARM-based SHMOBILE, the rspi driver builds and works fine without the
DMA controller driver, hence relax the dependencies.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: NMark Brown <broonie@linaro.org>

There is no need to force selection of TI EDMA DMA engine
driver when DaVinci SPI driver is selected. The driver
builds just fine even with CONFIG_TI_EDMA disabled.

Forcing this selection causes warnings of the sort:

warning: (ARCH_KEYSTONE && SPI_DAVINCI) selects TI_EDMA which has unmet direct dependencies (DMADEVICES && (ARCH_DAVINCI || ARCH_OMAP || ARCH_KEYSTONE))

This reverts commit b5f14330.
Reported-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NMark Brown <broonie@linaro.org>
Reviewed-by: NThierry Reding <treding@nvidia.com>

Add a driver for the High Speed SPI controller found on newer BCM63XX SoCs.

It does feature some new modes like 3-wire or dual spi, but neither of it
is currently implemented.
Signed-off-by: NJonas Gorski <jogo@openwrt.org>
Signed-off-by: NMark Brown <broonie@linaro.org>

This helps increasing build testing coverage.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NSimon Horman <horms@verge.net.au>
Signed-off-by: NMark Brown <broonie@linaro.org>

The legacy S3C64xx DMA driver has been removed, DMA support on
S3C64xx is provided only by the generic PL08x driver.

This patch modifies the Kconfig entry of spi-s3c64xx driver, which
relies on availability of DMA, to always select the S3C64XX_PL080
symbol.
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

With support for amba-pl08x driver, on S3C64xx the generic DMA engine
API can be used instead of the private s3c-dma interface.
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

It's not reliably available.
Signed-off-by: NMark Brown <broonie@linaro.org>

Replace all symbols by simple dependency PLAT_SAMSUNG.
Signed-off-by: NMateusz Krawczuk <m.krawczuk@partner.samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

The R8A7790 has QSPI module which is very similar to RSPI.
This patch adds into RSPI module together to supports QSPI module.
Signed-off-by: NHiep Cao Minh <cm-hiep@jinso.co.jp>
Signed-off-by: NMark Brown <broonie@linaro.org>

 - improve dependencies using COMPILE_TEST
 - fix a typo
 - drop platform_set_drvdata(pdev, NULL) in error path of probe
 - make MODULE_LICENSE match the header
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NMark Brown <broonie@linaro.org>

After the last architecture switched to generic hard irqs the config
options HAVE_GENERIC_HARDIRQS & GENERIC_HARDIRQS and the related code
for !CONFIG_GENERIC_HARDIRQS can be removed.
Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>

The patch add basic support for the quad spi controller.

QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.

The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).

Test details:
-------------
Tested this on dra7 board.
Test1: Ran mtd_stesstest for 40000 iterations.
   - All iterations went through without failure.
Test2: Use mtd utilities:
  - flash_erase to erase the flash device
  - mtd_debug read to read data back.
  - mtd_debug write to write to the data flash.
 diff between the write and read data shows zero.

Acked-by: Felipe Balbi<balbi@ti.com>
Reviewed-by: Felipe Balbi<balbi@ti.com>
Signed-off-by: NSourav Poddar <sourav.poddar@ti.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

The serial peripheral interface (SPI) module implemented on Freescale Vybrid
platform provides a synchronous serial bus for communication between Vybrid
and the external peripheral device.
The SPI supports full-duplex, three-wire synchronous transfer, has TX/RX FIFO
with depth of four entries.

This driver is the SPI master mode driver and has been tested on Vybrid
VF610TWR board.
Signed-off-by: NAlison Wang <b18965@freescale.com>
Signed-off-by: NChao Fu  <b44548@freescale.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NMark Brown <broonie@linaro.org>

It now needs the architecture dependant DMA driver.
Signed-off-by: NMark Brown <broonie@linaro.org>

Now that DMA support has been added to the driver it needs the
architecture DMA driver to be built in order to link.
Signed-off-by: NMark Brown <broonie@linaro.org>

Enable the build of drivers which don't have any real build time
dependency on their architecture or platform with COMPILE_TEST,
providing better build time coverage.
Signed-off-by: NMark Brown <broonie@linaro.org>

Keystone2 SOCs share the SPI IP block with DaVinci based SOCs. Update
the config bits so that its usable on Keystone2 based SOCs.
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

The filter function used by the rspi driver is part of the DMAE controller
driver so if the DMA controller driver is somehow disabled then the rspi
driver will fail to build.
Signed-off-by: NMark Brown <broonie@linaro.org>

New spi controller(version 3) is integrated into Blackfin
60x processor. Comparing to bf5xx spi controller, we support
32 bits word size and independent receive and transmit DMA
channels now. Also mode 0 and 2 (CPHA = 0) can get fully
supported becasue cs line may be controlled by the software.
Signed-off-by: NScott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

I got a build error today that made me realize that it is not
possible to build a kernel for a SiRF platform without enabling
CONFIG_PRIMA2, since a lot of common code depends on CONFIG_PRIMA2.

This fixes all occurences that appear like common SiRF code.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NWolfram Sang <wsa@the-dreams.de>
Acked-by: NMark Brown <broonie@linaro.org>
Acked-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: NBarry Song <Baohua.Song@csr.com>
Acked-by: NMike Turquette <mturquette@linaro.org>

CAVIUM_OCTEON_SOC most place we used to use CPU_CAVIUM_OCTEON.  This
allows us to CPU_CAVIUM_OCTEON in places where we have no OCTEON SOC.

Remove CAVIUM_OCTEON_SIMULATOR as it doesn't really do anything, we can
get the same configuration with CAVIUM_OCTEON_SOC.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-ide@vger.kernel.org
Cc: linux-edac@vger.kernel.org
Cc: linux-i2c@vger.kernel.org
Cc: netdev@vger.kernel.org
Cc: spi-devel-general@lists.sourceforge.net
Cc: devel@driverdev.osuosl.org
Cc: linux-usb@vger.kernel.org
Acked-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: NWolfram Sang <wsa@the-dreams.de>
Acked-by: NMauro Carvalho Chehab <mchehab@redhat.com>
Patchwork: https://patchwork.linux-mips.org/patch/5295/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

GENERIC_GPIO is now equivalent to GPIOLIB and features that depended on
GENERIC_GPIO can now depend on GPIOLIB to allow removal of this option.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>

Add SPI driver for NVIDIA's Tegra114 SPI controller. This controller
is different than the older SoCs SPI controller in internal design as
well as register interface.

This driver supports the:
- non DMA based transfer for smaller transfer i.e. less than FIFO depth.
- APB DMA based transfer for larger transfer i.e. more than FIFO depth.
- Clock gating through runtime PM callbacks.
- registration through DT only.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This adds support for the mostly register-compatible SPICTRL cores from the
GRLIB VHDL IP core library from Aeroflex Gaisler. They are normally running on
SPARC. A different entry in of_fsl_spi_match matches this core and indicates a
different hardware type that is used to set up different function pointers and
special cases.

The GRLIB core operates in cpu mode. The number of bits per word might be
limited. There might be native chipselects selected via a slave select
register. These differences to the FSL type cores, if present, are indicated by
a capabilities register. Other register and function differences exists but are
not relevant to the driver.
Acked-by: NAnton Vorontsov <anton@enomsg.org>
Signed-off-by: NAndreas Larsson <andreas@gaisler.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This makes the spi-fsl-spi driver usable in CPU mode outside of an FSL_SOC and
even an powerpc environment by moving CPM mode functionality to a separate file
that is only compiled and linked in an FSL_SOC environment and adding some
ifdefs to hide types and functions or provide alternatives.

For devicetree probing a "clock-frequency" property is used for clock frequency
instead of calls to FSL_SOC-specific functions.
Acked-by: NAnton Vorontsov <anton@enomsg.org>
Signed-off-by: NAndreas Larsson <andreas@gaisler.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

With this patch an allmodconfig finally builds on s390 again.

Fixes these build errors:

ERROR: "devm_request_threaded_irq" [drivers/spi/spi-altera.ko] undefined!
ERROR: "devm_request_threaded_irq" [drivers/media/platform/sh_veu.ko] undefined!
ERROR: "devm_request_threaded_irq" [drivers/dma/dw_dmac.ko] undefined!
Signed-off-by: NHeiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>

The BCM2835 contains two forms of SPI master controller (one known
simply as SPI0, and the other known as the "Universal SPI Master", in
the auxilliary block) and one form of SPI slave controller. This patch
adds support for the SPI0 controller.

This driver is taken from Chris Boot's repository at
git://github.com/bootc/linux.git rpi-linear
as of commit 6de2905 "spi-bcm2708: fix printf with spurious %s".
In the first SPI-related commit there, Chris wrote:

Thanks to csoutreach / A Robinson for his driver which I used as an
inspiration. You can find his version here:
http://piface.openlx.org.uk/raspberry-pi-spi-kernel-driver-available-for

Changes made during upstreaming:
* Renamed bcm2708 to bcm2835 as per upstream naming for this SoC.
* Removed support for brcm,realtime property.
* Increased transfer timeout to 30 seconds.
* Return IRQ_NONE from the IRQ handler if no interrupt was handled.
* Disable TA (Transfer Active) and clear FIFOs on a transfer timeout.
* Wrote device tree binding documentation.
* Request unnamed clock rather than "sys_pclk"; the DT will provide the
  correct clock.
* Assume that tfr->speed_hz and tfr->bits_per_word are always set in
  bcm2835_spi_start_transfer(), bcm2835_spi_transfer_one(), so no need
  to check spi->speed_hz or tft->bits_per_word.
* Re-ordered probe() to remove the need for temporary variables.
* Call clk_disable_unprepare() rather than just clk_unprepare() on probe()
  failure.
* Don't use devm_request_irq(), to ensure that the IRQ doesn't fire after
  we've torn down the device, but not unhooked the IRQ.
* Moved probe()'s call to clk_prepare_enable() so we can be sure the clock
  is enabled if the IRQ handler fires immediately.
* Remove redundant checks from bcm2835_spi_check_transfer() and
  bcm2835_spi_setup().
* Re-ordered IRQ handler to check for RXR before DONE. Added comments to
  ISR.
* Removed empty prepare/unprepare implementations.
* Removed use of devinit/devexit.
* Added BCM2835_ prefix to defines.
Signed-off-by: NChris Boot <bootc@bootc.net>
Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Intel Lynxpoint PCH Low Power Subsystem has two general purpose SPI
controllers that are LPSS_SSP compatible. These controllers are enumerated
from ACPI namespace with ACPI IDs INT33C0 and INT33C1.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: NLu Cao <lucao@marvell.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

To be able to use DMA with this driver on non-PXA platforms we implement
support for the generic DMA engine API. This lets user to use different DMA
engines with little or no modification to the driver.

Request lines and channel numbers can be passed to the driver from the
platform specific data.

The DMA engine implementation will be selected by default even on PXA
platform. User can select the legacy DMA API by enabling Kconfig option
CONFIG_SPI_PXA2XX_PXADMA.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Tested-by: NLu Cao <lucao@marvell.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

The PXA SPI driver uses PXA platform specific private DMA implementation
which does not work on non-PXA platforms. In order to use this driver on
other platforms we break out the private DMA implementation into a separate
file that gets compiled only when CONFIG_SPI_PXA2XX_PXADMA is set. The DMA
functions are stubbed out if there is no DMA implementation selected (i.e
we are building on non-PXA platform).

While we are there we can kill the dummy DMA bits in pxa2xx_spi.h as they
are not needed anymore for CE4100.

Once this is done we can add the generic DMA engine support to the driver
that allows usage of any DMA controller that implements DMA engine API.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Tested-by: NLu Cao <lucao@marvell.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

We are going to use it on 64-bit kernel on Intel Lynxpoint so make sure we
can build it into such kernel.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

The CONFIG_EXPERIMENTAL config item has not carried much meaning for a
while now and is almost always enabled by default. As agreed during the
Linux kernel summit, remove it from any "depends on" lines in Kconfigs.

CC: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NKees Cook <keescook@chromium.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The MSIOF hardware block is used in the SH Mobile series as well, so we
add it here.
Signed-off-by: NBastian Hecht <hechtb@gmail.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This driver is obsolete and can't even be built anymore since the
platform it depends has been removed.

The STMP series is completely covered by the MXS platform these days, so
spi-mxs can be used instead.
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This patch add new driver for CLPS711X SPI master controller.
Due to platform limitations driver supports only 8 bit transfer mode.
Chip select control is handled via GPIO.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

NVIDIA's Tegra20 have the SPI (SFLASH) controller to
interface with spi flash device which is used for system
boot. Add the spi driver for this controller.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Tegra20/Tegra30 supports the spi interface through its SLINK
controller. Add spi driver for SLINK controller.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>