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  1. 22 10月, 2010 7 次提交
    • M
      tegra: add PCI Express support · 77ffc146
      由 Mike Rapoport 提交于 
      Change-Id: Ibd0bcd46895eb88952b9db29e1f68572d39aae01
Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Acked-by: NArnd Bergmann <arnd@arndb.de>
CC: Russell King <linux@arm.linux.org.uk>
CC: Gary King <GKing@nvidia.com>
Signed-off-by: NColin Cross <ccross@android.com>
      77ffc146
    • C
      [ARM] tegra: Add APB DMA support · 4de3a8fa
      由 Colin Cross 提交于 
      The APB DMA block handles DMA transfers to and from some peripherals
in the Tegra SOC.  It reads from sequential addresses on the memory
bus, and writes repeatedly to the same address on the APB bus.

Two transfer modes are supported, oneshot for transferring a known
size to or from a peripheral, and continuous for streaming data.
In continuous mode, a callback occurs when the buffer is half full
to allow the existing data to be handled and a new request queued.x

v2 changes:
	dma API no longer uses PTR_ERR
Signed-off-by: NErik Gilling <konkers@android.com>
Signed-off-by: NColin Cross <ccross@android.com>
      4de3a8fa
    • C
      [ARM] tegra: Add cpufreq support · 7056d423
      由 Colin Cross 提交于 
      Implement cpufreq support for the Tegra SOC.  DVFS is handled by the
core virtual cpu clock.  The frequencies of the two cores are tied
together, the highest frequency requested by either core determines
the actual frequency.
Signed-off-by: NColin Cross <ccross@android.com>
      7056d423
    • C
      [ARM] tegra: clock: Add dvfs support, bug fixes, and cleanups · 71fc84cc
      由 Colin Cross 提交于 
      - Add drivers to clock lookup table
- Add new pll_m entries
- Support I2C U16 divider
- Fix rate reporting on 32.768kHz clock
- Call propagate rate only if set_rate succeeds
- Add support for audio_sync clock
- Add 24MHz to PLLA frequency list
- Correct i2s1/2/spdifout mux
- Add suspend support
- Fix enable/disable parent clocks in set_parent
- Add max_rate parameter to all clocks
- DVFS support
- Add virtual cpu clock with dvfs
- Support clk_round_rate
- Fix requesting very high periph frequencies
- Add quirks for PLLU:
   PLLU is slightly different from the rest of the PLLs.  The
   lock enable bit is at bit 22 instead of 18 in the MISC
   register, and the post divider field is a single bit with
   reversed values from other PLLs.
- Simplify recalculating clock rates
- Fix UART divider flags
- Remove unused clock ops
Signed-off-by: NColin Cross <ccross@android.com>
      71fc84cc
    • C
      [ARM] tegra: Add support for reading fuses · 73625e3e
      由 Colin Cross 提交于 
      The Tegra SOC contains fuses to identify the CPU type and
bin, and a unique id.  The CPU info is required to determine
the correct voltages for each cpu and core frequency.
Signed-off-by: NColin Cross <ccross@android.com>
      73625e3e
    • C
      [ARM] tegra: pinmux: add safe values, move tegra2, add suspend · c5f04b8d
      由 Colin Cross 提交于 
      - the reset values for some pin groups in the tegra pin mux can result in
functional errors due to conflicting with actively-configured pin groups
muxing from the same controller. this change adds a known safe, non-
conflicting mux for every pin group, which can be used on platforms
where the pin group is not routed to any peripheral

- also add each pin group's I/O voltage rail, to enable platform code to
map from the pin groups used by each interface to the regulators used
for dynamic voltage control

- add routines to individually configure the tristate, pin mux and pull-
ups for a pingroup_config array, so that it is possible to program
individual values at run-time without modifying other values.
this allows driver power-management code to reprogram individual
interfaces into lower power states during idle / suspend, or to
reprogram the pin mux to support multiple physical busses per
internal controller (e.g., sharing a single I2C or SPI controller
across multiple pin groups)

- move chip-specific data like pingroups and drive-pingroups
out of the common code and into chip-specific code

- fix debug output for group with no pullups

- add a TEGRA_MUX_SAFE function.  Setting a pingroup to TEGRA_MUX_SAFE
will automatically select a mux setting that is guaranteed not to
conflict with any of the hardware blocks.
Signed-off-by: NGary King <gking@nvidia.com>
      c5f04b8d
    • C
      [ARM] tegra: Add legacy irq support · 8726e4f5
      由 Colin Cross 提交于 
      The "legacy irq controller" duplicates the functionality of the GIC,
but remains powered during the cpu suspend and idle modes that power
down the CPU and the GIC.
Signed-off-by: NColin Cross <ccross@android.com>
      8726e4f5
  3. 06 8月, 2010 8 次提交