1. 25 11月, 2014 1 次提交
    • M
      arm64: topology: Fix handling of multi-level cluster MPIDR-based detection · 1cefdaea
      Mark Brown 提交于
      The only requirement the scheduler has on cluster IDs is that they must
      be unique.  When enumerating the topology based on MPIDR information the
      kernel currently generates cluster IDs by using the first level of
      affinity above the core ID (either level one or two depending on if the
      core has multiple threads) however the ARMv8 architecture allows for up
      to three levels of affinity.  This means that an ARMv8 system may
      contain cores which have MPIDRs identical other than affinity level
      three which with current code will cause us to report multiple cores
      with the same identification to the scheduler in violation of its
      uniqueness requirement.
      
      Ensure that we do not violate the scheduler requirements on systems that
      uses all the affinity levels by incorporating both affinity levels two
      and three into the cluser ID when the cores are not threaded.
      
      While no currently known hardware uses multi-level clusters it is better
      to program defensively, this will help ease bringup of systems that have
      them and will ensure that things like distribution install media do not
      need to be respun to replace kernels in order to deploy such systems.
      In the worst case the system will work but perform suboptimally until a
      kernel modified to handle the new topology better is installed, in the
      best case this will be an adequate description of such topologies for
      the scheduler to perform well.
      Signed-off-by: NMark Brown <broonie@linaro.org>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      1cefdaea
  2. 09 7月, 2014 1 次提交
  3. 17 5月, 2014 2 次提交
  4. 04 3月, 2014 1 次提交
    • M
      arm64: topology: Implement basic CPU topology support · f6e763b9
      Mark Brown 提交于
      Add basic CPU topology support to arm64, based on the existing pre-v8
      code and some work done by Mark Hambleton.  This patch does not
      implement any topology discovery support since that should be based on
      information from firmware, it merely implements the scaffolding for
      integration of topology support in the architecture.
      
      No locking of the topology data is done since it is only modified during
      CPU bringup with external serialisation from the SMP code.
      
      The goal is to separate the architecture hookup for providing topology
      information from the DT parsing in order to ease review and avoid
      blocking the architecture code (which will be built on by other work)
      with the DT code review by providing something simple and basic.
      
      Following patches will implement support for interpreting topology
      information from MPIDR and for parsing the DT topology bindings for ARM,
      similar patches will be needed for ACPI.
      Signed-off-by: NMark Brown <broonie@linaro.org>
      Acked-by: NMark Rutland <mark.rutland@arm.com>
      [catalin.marinas@arm.com: removed CONFIG_CPU_TOPOLOGY, always on if SMP]
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      f6e763b9