- 16 7月, 2016 1 次提交
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由 Philipp Zabel 提交于
We can't detect the FXEN (fiber mode) bootstrap pin, so configure it via a boolean device tree property "micrel,fiber-mode". If it is enabled, auto-negotiation is not supported. The only available modes are 100base-fx (full duplex and half duplex). Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 22 11月, 2014 3 次提交
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由 Johan Hovold 提交于
Add "micrel,rmii-reference-clock-select-25-mhz" to Micrel ethernet PHY binding documentation. This property is needed to properly describe some revisions of Micrel PHYs which has the function of this configuration bit inverted so that setting it enables 25 MHz rather than 50 MHz clock mode. Note that a clock reference ("rmii-ref") is still needed to actually select either mode. Cc: devicetree@vger.kernel.org Signed-off-by: NJohan Hovold <johan@kernel.org> Acked-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Johan Hovold 提交于
Reduce indentation of Micrel PHY binding documentations somewhat. Also fix "reference input clock" typo while at it. Cc: devicetree@vger.kernel.org Signed-off-by: NJohan Hovold <johan@kernel.org> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Johan Hovold 提交于
Micrel KSZ8081 and KSZ8091 PHYs have the RMII Reference Clock Select bit, which is used to select 25 or 50 MHz clock mode. Note that on some revisions of the PHY (e.g. KSZ8081RND) the function of this bit is inverted so that setting it enables 25 rather than 50 MHz mode. Add a new device-tree property "micrel,rmii-reference-clock-select-25-mhz" to describe this. Signed-off-by: NJohan Hovold <johan@kernel.org> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 13 11月, 2014 1 次提交
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由 Johan Hovold 提交于
Enable led-mode configuration for KSZ8081 and KSZ8091. Signed-off-by: NJohan Hovold <johan@kernel.org> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 11 10月, 2014 1 次提交
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由 Sascha Hauer 提交于
The KSZ8021 and KSZ8031 support RMII reference input clocks of 25MHz and 50MHz. Both PHYs differ in the default frequency they expect after reset. If this differs from the actual input clock, then register 0x1f bit 7 must be changed. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 27 2月, 2014 1 次提交
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由 Ben Dooks 提交于
Add support for the led-mode property for the following PHYs which have a single LED mode configuration value. KSZ8001 and KSZ8041 which both use register 0x1e bits 15,14 and KSZ8021, KSZ8031 and KSZ8051 which use register 0x1f bits 5,4 to control the LED configuration. Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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