Check if we can switch the mclk during the vblank time otherwise
we may get artifacts on the screen when the mclk changes.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Check if we can switch the mclk during the vblank time otherwise
we may get artifacts on the screen when the mclk changes.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Check if we can switch the mclk during the vblank time otherwise
we may get artifacts on the screen when the mclk changes.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Check if we can switch the mclk during the vblank time otherwise
we may get artifacts on the screen when the mclk changes.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Check if we can switch the mclk during the vblank time otherwise
we may get artifacts on the screen when the mclk changes.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

If the vblank time is too short to adjust mclk,
assume multiple displays (no mclk adjustments).
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Required for checking vblank time for mclk changes.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Looks like a remnant from an old rebase.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Check the driver state rather than the register as the
crtc registers may not be enabled yet.

Should fix:
https://bugzilla.kernel.org/show_bug.cgi?id=60510
https://bugs.freedesktop.org/show_bug.cgi?id=66651Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

"drm/nve0-/gr: some new gpc registers can have multiple copies"
5ee86c41 caused a regression for nvc0, because the bit indicating last
transfer has occured was no longer set, resulting in random system lockups.
Reported-by: NRonald Uitermark <ronald645@gmail.com>
Tested-by: NRonald Uitermark <ronald645@gmail.com>
Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Reported-by: NMaarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Allows you to force the selected performance level via sysfs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Allows you to force the selected performance level via sysfs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Allows you to force the selected performance level via sysfs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Allows you to force a performance level via sysfs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Allows you to limit the selected power levels via sysfs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This allows you to force specific power levels within a power
state.  Due to hardware restrictions between generations, the
interface is limited to the following 3 selections:

auto: all levels enabled
low: forced to the lowest power level
high: forced to the highest power level
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

r1xx asics have a slightly different surface register
setup compared to newer asics.  There is no specific
enable bit for macro tiling, rather, to disable macro
tiling, you need to set the surface pitch to 0.

With this fixed, the special rn50 handling can go.
Noticed-by: NMark Kettenis <mark.kettenis@xs4all.nl>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Certain older rv770 asics have both a performance and
a 3D performance state rather than just multiple performance
levels in the state power state.  The current code would
select the performance state rather than the 3D performance
state when the "performance" profile was selected.  This change
switches to the "balanced" profile by default which ends up being
the internal performance profile.  When the user selects the
"performance" profile, it selects the internal 3D performance
state so the user can select the higher performance modes.

For most asics this changes nothing.  For certain rv770 asics
with static performance and 3D performance states, this allows
you to select between then using by selecting the "balanced"
and "performance" dpm profiles.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fix patching of vddc values for SI and enable manually forcing
clocks to default levels as per NI.

This improves the out of the box performance with SI asics.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

We can use prime helpers instead.
Signed-off-by: NJoonyoung Shim <jy0922.shim@samsung.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Instead of using the dma_buf functionality for GEM CMA, we can use prime
helpers if we can provide low-level hook functions for GEM CMA.
Signed-off-by: NJoonyoung Shim <jy0922.shim@samsung.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

This adds to call low-level mmap() from prime helpers.
Signed-off-by: NJoonyoung Shim <jy0922.shim@samsung.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

The drm_gem_map_detach() can be called with sgt is NULL.
Signed-off-by: NJoonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

The DU requires a 16 pixels pitch alignement. Make sure dumb buffers are
allocated with the correct pitch, and validate the pitch when creating
frame buffers.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Handle error cases correctly.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

This is the nva3 counterpart to commit beba44b1 (drm/nv84/disp: Fix
HDMI audio regression). The regression happened as a result of
refactoring in commit 8e9e3d2d (drm/nv84/disp: move hdmi control into
core).
Reported-and-tested-by: NMax Baldwin <archerseven@gmail.com>
Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org

The commit

   commit 476e84e1
   Author: Ben Skeggs <bskeggs@redhat.com>
   Date:   Mon Feb 11 09:24:23 2013 +1000

       drm/nv50-/disp: initial supervisor support for off-chip encoders

changed the write mask in one of the interrupt functions for on-chip encoders,
causing a regression in certain VGA dual-head setups. This commit reintroduces
the mask thus resolving the regression

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66129Reported-and-Tested-by: NYves-Alexis <corsac@debian.org>
Cc: stable@vger.kernel.org [3.9+]
CC: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: NEmil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Page tables on nv50 take 48kB, which can be hard to allocate in one piece.
Let's use vmalloc.
Signed-off-by: NMarcin Slusarz <marcin.slusarz@gmail.com>
Cc: stable@vger.kernel.org [3.7+]
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

NVC1/NVD9 are the only chipsets that should have anything different
happen on them after this.  We previously weren't doing these
register modifications, and NVIDIA do.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

This can be generalised and used on GK104 (probably even GF117), but lets
just make it work for now.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>