1. 07 11月, 2007 1 次提交
  2. 30 10月, 2007 1 次提交
    • P
      sh: Correct pte_page() breakage. · afca0357
      Paul Mundt 提交于
      As noted by David:
      
      pte_page() is a macro defined as follows;
      
          include/asm-sh/pgtable.h
          #define pte_page(x)    phys_to_page(pte_val(x)&PTE_PHYS_MASK)
      
          include/asm-sh/page.h
          #define phys_to_page(phys)    (pfn_to_page(phys >> PAGE_SHIFT))
      
      So as you can see the phys_to_page() macro doesn't wrap the 'phys'
      parameter in parentheses so we end up with;
      
          pte_val(x)&PTE_PHYS_MASK >> PAGE_SHIFT
      
      Which is not what we wanted as '>>' has a higher precedence than bitwise
      AND. I dug into the git repository and I believe this bug was added with
      this commit (104b8dea);
      
      2006-03-27 KAMEZAWA Hiroyuki [PATCH] unify pfn_to_page: sh pfn_to_page
      
      -#define phys_to_page(phys)     (mem_map + (((phys)-__MEMORY_START) >>
      PAGE_SHIFT))
      -#define page_to_phys(page)     (((page - mem_map) << PAGE_SHIFT) +
      __MEMORY_START)
      +#define phys_to_page(phys)     (pfn_to_page(phys >> PAGE_SHIFT))
      +#define page_to_phys(page)     (page_to_pfn(page) << PAGE_SHIFT)
      Reported-by: NDavid ADDISON <david.addison@st.com>
      Reported-by: NKAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      afca0357
  3. 21 9月, 2007 2 次提交
    • P
      sh: Fix up extended mode TLB for SH-X2+ cores. · d04a0f79
      Paul Mundt 提交于
      The extended mode TLB requires both 64-bit PTEs and a 64-bit pgprot,
      correspondingly, the PGD also has to be 64-bits, so fix that up.
      
      The kernel and user permission bits really are decoupled in early
      cuts of the silicon, which means that we also have to set corresponding
      kernel permissions on user pages or we end up with user pages that the
      kernel simply can't touch (!).
      
      Finally, with those things corrected, really enable MMUCR.ME and
      correct the PTEA value (this simply needs to be the upper 32-bits
      of the PTE, with the size and protection bit encoding).
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      d04a0f79
    • P
      sh: Support explicit L1 cache disabling. · e7bd34a1
      Paul Mundt 提交于
      This reworks the cache mode configuration in Kconfig, and allows for
      explicit selection of write-back/write-through/off configurations.
      All of the cache flushing routines are optimized away for the off
      case.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      e7bd34a1
  4. 08 6月, 2007 3 次提交
  5. 07 5月, 2007 1 次提交
  6. 13 2月, 2007 1 次提交
  7. 06 12月, 2006 1 次提交
    • P
      sh: Preliminary support for SH-X2 MMU. · 21440cf0
      Paul Mundt 提交于
      This adds some preliminary support for the SH-X2 MMU, used by
      newer SH-4A parts (particularly SH7785).
      
      This MMU implements a 'compat' mode with SH-X MMUs and an
      'extended' mode for SH-X2 extended features. Extended features
      include additional page sizes (8kB, 4MB, 64MB), as well as the
      addition of page execute permissions.
      
      The extended mode attributes are placed in a second data array,
      which requires us to switch to 64-bit PTEs when in X2 mode.
      
      With the addition of the exec perms, we also overhaul the mmap
      prots somewhat, now that it's possible to handle them more
      intelligently.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      21440cf0
  8. 27 9月, 2006 8 次提交
  9. 21 9月, 2006 1 次提交
  10. 09 9月, 2006 1 次提交
  11. 26 4月, 2006 1 次提交
  12. 28 3月, 2006 1 次提交
  13. 07 11月, 2005 1 次提交
    • P
      [PATCH] sh: Drop hp690 discontig support · 65463b73
      Paul Mundt 提交于
      There was only one board using this (hp690 specifically), and it just so
      happens that it's only physically discontiguous at the "normal" P1 offset.  If
      we bump up the P1 offset, it's possible to hit a shadowed region of memory
      where we suddenly become magically contiguous.
      
      As people have been using this shadowed region workaround for quite some time
      (and without any adverse effects), it's time to drop the left over discontig
      bits that no longer have any practical use (it was always very much
      hp690-centric to begin with).
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      65463b73
  14. 05 9月, 2005 1 次提交
  15. 22 6月, 2005 1 次提交
    • D
      [PATCH] Hugepage consolidation · 63551ae0
      David Gibson 提交于
      A lot of the code in arch/*/mm/hugetlbpage.c is quite similar.  This patch
      attempts to consolidate a lot of the code across the arch's, putting the
      combined version in mm/hugetlb.c.  There are a couple of uglyish hacks in
      order to covert all the hugepage archs, but the result is a very large
      reduction in the total amount of code.  It also means things like hugepage
      lazy allocation could be implemented in one place, instead of six.
      
      Tested, at least a little, on ppc64, i386 and x86_64.
      
      Notes:
      	- this patch changes the meaning of set_huge_pte() to be more
      	  analagous to set_pte()
      	- does SH4 need s special huge_ptep_get_and_clear()??
      Acked-by: NWilliam Lee Irwin <wli@holomorphy.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      63551ae0
  16. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4