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  1. 08 12月, 2006 4 次提交
    • N
      [ARM] 3980/1: extend the ARM Versatile sched_clock implementation from 32 to 63 bit · 752bee17
      由 Nicolas Pitre 提交于 
       period

This provides a 63 bit clock counter guaranteed to be monotonic over a
period of 35583 days instead of a clock wrap every 179 seconds, as long
as sched_clock() is called at least once every 89 seconds.  This should
not be a problem in practice, although a kernel timer could be scheduled
every 80 seconds for example simply to call sched_clock() making sure
top bits are always synchronized if need be.
Signed-off-by: NNicolas Pitre <nico@cam.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      752bee17
    • N
      [ARM] 3979/1: extend the SA11x0 sched_clock implementation from 32 to 63 bit period · 2f1675c1
      由 Nicolas Pitre 提交于 
      This provides a 63 bit clock counter guaranteed to be monotonic over a
period of 370 days instead of a clock wrap every 19.4 minutes, as long
as sched_clock() is called at least once every 9.7 minutes which
shouldn't be a problem in practice.
Signed-off-by: NNicolas Pitre <nico@cam.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      2f1675c1
    • N
      [ARM] 3978/1: macro to provide a 63-bit value from a 32-bit hardware counter · 838ccbc3
      由 Nicolas Pitre 提交于 
      This is done in a completely lockless fashion. Bits 0 to 31 of the count
are provided by the hardware while bits 32 to 62 are stored in memory.
The top bit in memory is used to synchronize with the hardware count
half-period.  When the top bit of both counters (hardware and in memory)
differ then the memory is updated with a new value, incrementing it when
the hardware counter wraps around.  Because a word store in memory is
atomic then the incremented value will always be in synch with the top
bit indicating to any potential concurrent reader if the value in memory
is up to date or not wrt the needed increment.  And any race in updating
the value in memory is harmless as the same value would be stored more
than once.
Signed-off-by: NNicolas Pitre <nico@cam.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      838ccbc3
    • N
      [ARM] 3611/4: optimize do_div() when divisor is constant · fa4adc61
      由 Nicolas Pitre 提交于 
      On ARM all divisions have to be performed "manually".  For 64-bit
divisions that may take more than a hundred cycles in many cases.

With 32-bit divisions gcc already use the recyprocal of constant
divisors to perform a multiplication, but not with 64-bit divisions.

Since the kernel is increasingly relying upon 64-bit divisions it is
worth optimizing at least those cases where the divisor is a constant.
This is what this patch does using plain C code that gets optimized away
at compile time.

For example, despite the amount of added C code, do_div(x, 10000) now
produces the following assembly code (where x is assigned to r0-r1):

	adr	r4, .L0
	ldmia	r4, {r4-r5}
	umull	r2, r3, r4, r0
	mov	r2, #0
	umlal	r3, r2, r5, r0
	umlal	r3, r2, r4, r1
	mov	r3, #0
	umlal	r2, r3, r5, r1
	mov	r0, r2, lsr #11
	orr	r0, r0, r3, lsl #21
	mov	r1, r3, lsr #11
	...
.L0:
	.word	948328779
	.word	879609302

which is the fastest that can be done for any value of x in that case,
many times faster than the __do_div64 code (except for the small x value
space for which the result ends up being zero or a single bit).

The fact that this code is generated inline produces a tiny increase in
.text size, but not significant compared to the needed code around each
__do_div64 call site this code is replacing.

The algorithm used has been validated on a 16-bit scale for all possible
values, and then recodified for 64-bit values.  Furthermore I've been
running it with the final BUG_ON() uncommented for over two months now
with no problem.

Note that this new code is compiled with gcc versions 4.0 or later.
Earlier gcc versions proved themselves too problematic and only the
original code is used with them.
Signed-off-by: NNicolas Pitre <nico@cam.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      fa4adc61
  3. 30 11月, 2006 5 次提交
  5. 29 11月, 2006 24 次提交
  7. 28 11月, 2006 7 次提交