提交 · 749cf76c5a363e1383108a914ea09530bfa0bd43 · openeuler / raspberrypi-kernel

24 1月, 2013 3 次提交

KVM: ARM: Initial skeleton to compile KVM support · 749cf76c

由 Christoffer Dall 提交于 1月 20, 2013

Targets KVM support for Cortex A-15 processors.

Contains all the framework components, make files, header files, some
tracing functionality, and basic user space API.

Only supported core is Cortex-A15 for now.

Most functionality is in arch/arm/kvm/* or arch/arm/include/asm/kvm_*.h.
Reviewed-by: NWill Deacon <will.deacon@arm.com>
Reviewed-by: NMarcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: NRusty Russell <rusty@rustcorp.com.au>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NChristoffer Dall <c.dall@virtualopensystems.com>

749cf76c

ARM: Section based HYP idmap · 9e9a367c

由 Christoffer Dall 提交于 1月 20, 2013

Add a method (hyp_idmap_setup) to populate a hyp pgd with an
identity mapping of the code contained in the .hyp.idmap.text
section.

Offer a method to drop this identity mapping through
hyp_idmap_teardown.

Make all the above depend on CONFIG_ARM_VIRT_EXT and CONFIG_ARM_LPAE.
Reviewed-by: NWill Deacon <will.deacon@arm.com>
Reviewed-by: NMarcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NChristoffer Dall <c.dall@virtualopensystems.com>

9e9a367c

ARM: Add page table and page defines needed by KVM · cc577c26

由 Christoffer Dall 提交于 1月 20, 2013

KVM uses the stage-2 page tables and the Hyp page table format,
so we define the fields and page protection flags needed by KVM.

The nomenclature is this:
 - page_hyp:        PL2 code/data mappings
 - page_hyp_device: PL2 device mappings (vgic access)
 - page_s2:         Stage-2 code/data page mappings
 - page_s2_device:  Stage-2 device mappings (vgic access)
Reviewed-by: NWill Deacon <will.deacon@arm.com>
Reviewed-by: NMarcelo Tosatti <mtosatti@redhat.com>
Christoffer Dall <c.dall@virtualopensystems.com>

cc577c26

19 1月, 2013 1 次提交

ARM: perf: simplify __hw_perf_event_init err handling · 9dcbf466

由 Mark Rutland 提交于 1月 18, 2013

Currently __hw_perf_event_init has an err variable that's ignored right
until the end, where it's initialised, conditionally set, and then used
as a boolean flag deciding whether to return another error code.

This patch removes the err variable and simplifies the associated error
handling logic.
Signed-off-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>

9dcbf466

18 1月, 2013 2 次提交

ARM: perf: remove unnecessary checks for idx < 0 · 8f3b90b5

由 Mark Rutland 提交于 1月 18, 2013

We currently check for hwx->idx < 0 in armpmu_read and armpmu_del
unnecessarily. The only case where hwc->idx < 0 is when armpmu_add
fails, in which case the event's state is set to
PERF_EVENT_STATE_INACTIVE.

The perf core will not attempt to read from an event in
PERF_EVENT_STATE_INACTIVE, and so the check in armpmu_read is
unnecessary. Similarly, if perf core cannot add an event it will not
attempt to delete it, so the WARN_ON in armpmu_del is unnecessary.

This patch removes these two redundant checks.
Signed-off-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>

8f3b90b5

ARM: perf: handle armpmu_register failing · 76b8a0e4

由 Mark Rutland 提交于 1月 18, 2013

Currently perf_pmu_register may fail for several reasons (e.g. being
unable to allocate memory for the struct device it associates with each
PMU), and while any error is propagated by armpmu_register, it is
ignored by cpu_pmu_device_probe and not propagated to the caller.  This
also results in a leak of a struct arm_pmu.

This patch adds cleanup if armpmu_register fails, and updates the info
messages to better differentiate this type of failure from a failure to
probe the PMU type from the hardware or dt.
Signed-off-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>

76b8a0e4

16 1月, 2013 1 次提交

ARM: perf: don't pretend to support counting of L1I writes · 40c390c7

由 Will Deacon 提交于 1月 16, 2013

ARM has a harvard cache architecture and cannot write directly to the
I-side.

This patch removes the L1I write events from the cache map (which
previously returned *read* events in many cases).
Reported-by: NMike Williams <michael.williams@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>

40c390c7

15 1月, 2013 1 次提交

ARM: perf: remove redundant NULL check on cpu_pmu · 1764c591

由 Will Deacon 提交于 1月 14, 2013

cpu_pmu has already been dereferenced before we consider invoking the
->reset function, so remove the redundant NULL check.
Reported-by: NCong Ding <dinggnu@gmail.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>

1764c591

11 1月, 2013 2 次提交

ARM: Use implementor and part defines from cputype.h · 3b953c9c

由 Christoffer Dall 提交于 12月 18, 2012

Instead of decoding implementor numbers, part numbers and Xscale
architecture masks inline in the pmu probing function, use defines
and accessor functions from cputype.h, which can also be shared by
other subsystems, such as KVM.
Signed-off-by: NChristoffer Dall <c.dall@virtualopensystems.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>

3b953c9c

ARM: Define CPU part numbers and implementors · 59530adc

由 Christoffer Dall 提交于 12月 18, 2012

Define implementor IDs, part numbers and Xscale architecture versions in
cputype.h. Also create accessor functions for reading the implementor,
part number, and Xscale architecture versions from the CPUID regiser.
Signed-off-by: NChristoffer Dall <c.dall@virtualopensystems.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>

59530adc

08 1月, 2013 10 次提交

ARM: clps711x: Fix bad merge of clockevents setup · 0e3a4a2e

由 Olof Johansson 提交于 1月 05, 2013

I mismerged a previous branch from Alexander, and accidentally left
in ARCH_USES_GETTIMEOFFSET. Remove it.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Cc: Alexander Shiyan <shc_work@mail.ru>

0e3a4a2e

ARM: highbank: save and restore L2 cache and GIC on suspend · 1ddda1cd