- 21 12月, 2011 3 次提交
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由 Alex Deucher 提交于
For supporting multiple CP ring buffers, async DMA engines and UVD. We still need a way to synchronize between engines. v2 initialize unused fence driver ring to avoid issue in suspend/unload Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NChristian König <deathsimple@vodafone.de> Reviewed-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Christian König 提交于
Better fix it before this obvious typo spreads even more. Signed-off-by: NChristian König <deathsimple@vodafone.de> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Christian König 提交于
Having registered debugfs files globally causes the files to not show up on the second, third etc.. card in the system. v2: fix crash on module unloading v3: fix space indentation Signed-off-by: NChristian König <deathsimple@vodafone.de> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 06 12月, 2011 1 次提交
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由 Konrad Rzeszutek Wilk 提交于
With the exception that we do not handle the AGP case. We only deal with PCIe cards such as ATI ES1000 or HD3200 that have been detected to only do DMA up to 32-bits. V2 force dma32 if we fail to set bigger dma mask V3 Rebase on top of no memory account changes (where/when is my delorean when i need it ?) V4 add debugfs entry is swiotlb is active not only if we are on dma 32bits only gpu CC: Dave Airlie <airlied@redhat.com> CC: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Reviewed-by: NJerome Glisse <jglisse@redhat.com>
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- 20 11月, 2011 1 次提交
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由 Marek Olšák 提交于
This adds a new optional chunk to the CS ioctl that specifies optional flags to the CS parser. Why this is useful is explained below. Note that some regs no longer need the NOP relocation packet if this feature is enabled. Tested on r300g and r600g with this flag disabled and enabled. Assume there are two contexts sharing the same mipmapped tiled texture. One context wants to render into the first mipmap and the other one wants to render into the last mipmap. As you probably know, the hardware has a MACRO_SWITCH feature, which turns off macro tiling for small mipmaps, but that only applies to samplers. (at least on r300-r500, though later hardware likely behaves the same) So we want to just re-set the tiling flags before rendering (writing packets), right? ... No. The contexts run in parallel, so they may set the tiling flags simultaneously and then fire their command streams also simultaneously. The last one setting the flags wins, the other one loses. Another problem is when one context wants to render into the first and the last mipmap in one CS. Impossible. It must flush before changing tiling flags and do the rendering into the smaller mipmaps in another CS. Yet another problem is that writing copy_blit in userspace would be a mess involving re-setting tiling flags to please the kernel, and causing races with other contexts at the same time. The only way out of this is to send tiling flags with each CS, ideally with each relocation. But we already do that through the registers. So let's just use what we have in the registers. Signed-off-by: NMarek Olšák <maraeo@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 11 11月, 2011 3 次提交
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由 Alex Deucher 提交于
On newer chips the number of clock modes per power state varies. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
The new power tables need to be handled differently when setting up the profiles. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Michel Dänzer 提交于
This was only the case if the GPU reset was triggered from the CS ioctl, otherwise other processes could happily enter the CS ioctl and wreak havoc during the GPU reset. This is a little complicated because the GPU reset can be triggered from the CS ioctl, in which case we're already holding the mutex, or from other call paths, in which case we need to lock the mutex. AFAICT the mutex API doesn't allow recursive locking or finding out the mutex owner, so we need to handle this with helper functions which allow recursive locking from the same process. Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Reviewed-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 04 11月, 2011 2 次提交
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由 Jerome Glisse 提交于
After GPU lockup VRAM gart table is unpinned and thus its pointer becomes unvalid. This patch move the unpin code to a common helper function and set pointer to NULL so that page update code can check if it should update GPU page table or not. That way bo still bound to GART can be unbound (pci_unmap_page for all there page) properly while there is no need to update the GPU page table. V2 move the test for null gart out of the loop, small optimization Signed-off-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Allow the user to override whether MSIs are enabled or not on supported ASICs. MSIs are disabled by default on IGP chips as they tend not to work. However certain IGP chips only seem to work with MSIs enabled. I suspect this is a chipset or bios issue, but I'm not sure what the proper fix is. This will at least make diagnosing and working around the problem much easier. See: https://bugs.freedesktop.org/show_bug.cgi?id=37679Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 02 11月, 2011 3 次提交
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由 Alex Deucher 提交于
The vram scratch was originally only used on some 7xx asics to work around a hw bug. Allocate the scratch page on all 6xx+ radeons and set the MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR to point to it. We shouldn't ever hit it since we limit the system aperture to vram or vram and AGP, but better safe than sorry. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Ilija Hadzic 提交于
radeon_driver_irq_preinstall_kms and radeon_driver_irq_uninstall_kms hard code the loop to 6 which happens to be the current maximum number of crtcs and hpd pins; if one day an ASIC with more crtcs (or hpd pins) comes out, this is a trouble waiting to happen. introduce constants for maximum CRTC count, maximum HPD pins count and maximum HDMI blocks count (per FIXME in radeon_irq structure) and correct the loops in radeon_driver_irq_preinstall_kms and radeon_driver_irq_uninstall_kms v2: take care of goofs pointed out by Alex Deucher Signed-off-by: NIlija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Move the TC flush before the texture setup to match mesa and the ddx. Also, move the TC flush into the texture setup function. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 28 10月, 2011 1 次提交
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由 Dave Airlie 提交于
This reverts commit d3ed7402. Further upstream discussion between Thomas and Marek decided this needed more work and driver specifics. So revert before it goes upstream. Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 18 10月, 2011 5 次提交
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由 Alex Deucher 提交于
r600-NI shared the same blit suspend code. Clean it up and make it a shared function. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NIlija Hadzic <ihadzic@research.bell-labs.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Ilija Hadzic 提交于
reorganize the code such that only the primitives (i.e., the functions that load the CP ring) are hardware specific; dynamically link the primitives in a (new) pointer structure inside r600_blit at blit initialization time so that the functions that control the blit operations can be made common for r600 and evergreen parts Signed-off-by: NIlija Hadzic <ihadzic@research.bell-labs.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Ilija Hadzic 提交于
Lots of new (and hopefully useful) benchmark. Load the driver with radeon_benchmark=<test_number> and enjoy. Among tests added are VRAM to VRAM blits and blits with buffer size sweeps. The latter can be from GTT to VRAM, VRAM to GTT, and VRAM to VRAM and there are two types of sweeps: powers of two and (probably more interesting) buffers sizes that correspond to common modes. Signed-off-by: NIlija Hadzic <ihadzic@research.bell-labs.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Andi Kleen 提交于
This shrinks the sizes of a lot of functions in the radeon driver dramatically. With a non force inline + -Os kernel this is default anyways. Cc: David Airlie <airlied@linux.ie> Signed-off-by: NAndi Kleen <ak@linux.intel.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Andi Kleen 提交于
With this patch I'm only about 50k larger with DRM debugging enables (why is that enabled by default?!?), and slightly smaller without. [airlied: moved r100.c additions to radeon_ring.c] Signed-off-by: NAndi Kleen <ak@linux.intel.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 10 10月, 2011 1 次提交
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由 Michael Witten 提交于
The value of RADEON_DEBUGFS_MAX_NUM_FILES has been used to specify the size of an array, each element of which looks like this: struct radeon_debugfs { struct drm_info_list *files; unsigned num_files; }; Consequently, the number of debugfs files may be much greater than RADEON_DEBUGFS_MAX_NUM_FILES, something that the current code ignores: if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { DRM_ERROR("Reached maximum number of debugfs files.\n"); DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); return -EINVAL; } This commit fixes this make, and accordingly renames: RADEON_DEBUGFS_MAX_NUM_FILES to: RADEON_DEBUGFS_MAX_COMPONENTS Signed-off-by: NMichael Witten <mfwitten@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 19 9月, 2011 1 次提交
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由 Alex Deucher 提交于
The BO blit code inconsistenly handled the page size. This wasn't an issue on system with 4k pages since the GPU's page size is 4k as well. Switch the driver blit callbacks to take num pages in GPU page units. Fixes lemote mipsel systems using AMD rs780/rs880 chipsets. v2: incorporate suggestions from Michel. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NMichel Dänzer <michel.daenzer@amd.com> Cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 01 9月, 2011 1 次提交
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由 Marek Olšák 提交于
The new DRM_RADEON_GEM_WAIT ioctl combines GEM_WAIT_IDLE and GEM_BUSY (there is a NO_WAIT flag to get the latter) with USAGE_READ and USAGE_WRITE flags to take advantage of the new ttm_bo_wait changes. Also bump the DRM version. Signed-off-by: NMarek Olšák <maraeo@gmail.com> Reviewed-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 27 7月, 2011 1 次提交
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由 Arun Sharma 提交于
This allows us to move duplicated code in <asm/atomic.h> (atomic_inc_not_zero() for now) to <linux/atomic.h> Signed-off-by: NArun Sharma <asharma@fb.com> Reviewed-by: NEric Dumazet <eric.dumazet@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: David Miller <davem@davemloft.net> Cc: Eric Dumazet <eric.dumazet@gmail.com> Acked-by: NMike Frysinger <vapier@gentoo.org> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 25 7月, 2011 1 次提交
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由 Benjamin Herrenschmidt 提交于
Just defining rdev->rmmio properly in the first place should do the trick. In some cases, the cast were also complete dups as the original variable was already of the right type. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 18 7月, 2011 1 次提交
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由 Alex Deucher 提交于
The 3D driver need to get the pipe to backend map to certain things. Add a query to get the info. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 24 6月, 2011 1 次提交
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由 Alex Deucher 提交于
A voltage value of 0xff01 requires that the driver look up the max voltage for the board based using the atom SetVoltage command table. Setting the proper voltage should fix stability on some newer asics. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 09 6月, 2011 1 次提交
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由 Alex Deucher 提交于
Filter out modes that are higher than the max pixel clock. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 13 4月, 2011 2 次提交
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由 Alex Deucher 提交于
Change vddci as well as vddc when changing power modes on evergreen/ni. Also, properly set vddci on boot up for ni cards. The vbios only sets the limited clocks and voltages on boot until the mc ucode is loaded. This should fix stability problems on some btc cards. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
This is needed for setting voltages other than vddc. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 31 3月, 2011 1 次提交
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由 Lucas De Marchi 提交于
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: NLucas De Marchi <lucas.demarchi@profusion.mobi>
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- 14 3月, 2011 1 次提交
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由 Dave Airlie 提交于
So we used to use lpfn directly to restrict VRAM when we couldn't access the unmappable area, however this was removed in 93225b0d as it also restricted the gtt placements. However it was only later noticed that this broke on some hw. This removes the active_vram_size, and just explicitly sets it when it changes, TTM/drm_mm will always use the real_vram_size, and the active vram size will change the TTM size used for lpfn setting. We should re-work the fpfn/lpfn to per-placement at some point I suspect, but that is too late for this kernel. Hopefully this addresses: https://bugs.freedesktop.org/show_bug.cgi?id=35254 v2: fix reported useful VRAM size to userspace to be correct. Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 03 3月, 2011 3 次提交
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由 Alex Deucher 提交于
Cayman is different enough from evergreen to warrant it's own functions. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Cayman asics have 3 ring buffers: ring 0 supports both gfx and compute rings 1 and 2 are compute only At the moment we only support ring 0. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
This may some work to get accel going. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 23 2月, 2011 5 次提交
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由 Daniel Vetter 提交于
Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Daniel Vetter 提交于
Now all the asic specific stuff ist mostly hid in radeon_asic.* Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Daniel Vetter 提交于
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Daniel Vetter 提交于
... and switch it to container_of upcasting. v2: converted new pageflip code-paths. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Daniel Vetter 提交于
Unconditionally initialize the drm gem object - it's not worth the trouble not to for the few kernel objects. This patch only changes the place of the drm gem object, access is still done via pointers. v2: Uncoditionally align the size in radeon_bo_create. At least the r600/evergreen blit code didn't to this, angering the paranoid gem code. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 19 2月, 2011 1 次提交
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由 Konrad Rzeszutek Wilk 提交于
If the TTM layer has used the DMA API to setup pages that are TTM_PAGE_FLAG_DMA32 (look at patch titled: "ttm: Utilize the dma_addr_t array for pages that are to in DMA32 pool."), lets use it when programming the GART in the PCIe type cards. This patch skips doing the pci_map_page (and pci_unmap_page) if there is a DMA addresses passed in for that page. If the dma_address is zero (or DMA_ERROR_CODE), then we continue on with our old behaviour. [v2: Fixed an indentation problem, added reviewed-by tag] [v3: Added Acked-by Jerome] Acked-by: NJerome Glisse <j.glisse@gmail.com> Reviewed-by: NThomas Hellstrom <thomas@shipmail.org> Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Tested-by: NIan Campbell <ian.campbell@citrix.com>
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