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  1. 27 2月, 2010 19 次提交
  3. 26 2月, 2010 1 次提交
    • T
      x86/PCI: Prevent mmconfig memory corruption · bb8d4133
      由 Thomas Gleixner 提交于 
      commit ff097ddd (x86/PCI: MMCONFIG: manage pci_mmcfg_region as a
list, not a table) introduced a nasty memory corruption when
pci_mmcfg_list is empty.

pci_mmcfg_check_end_bus_number() dereferences pci_mmcfg_list.prev even
when the list is empty. The following write hits some variable near to
pci_mmcfg_list.

Further down a similar problem exists, where cfg->list.next is
dereferenced unconditionally and a comparison with some variable near
to pci_mmcfg_list happens.

Add a check for the last element into the for_each_entry() loop and
remove all the other crappy logic which is just a leftover of the old
array based code which was replaced by the list conversion.
Reported-by: NIngo Molnar <mingo@elte.hu>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Bjorn Helgaas <bjorn.helgaas@hp.com>
Cc: Yinghai Lu <yinghai@kernel.org>
Cc: stable@kernel.org
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      bb8d4133
  5. 25 2月, 2010 1 次提交
  7. 24 2月, 2010 6 次提交
  9. 23 2月, 2010 6 次提交
  11. 22 2月, 2010 1 次提交
  13. 21 2月, 2010 1 次提交
    • R
      ARM: allow alignment fault mode to be configured at kernel boot · d944d549
      由 Russell King 提交于 
      Some glibc versions intentionally create lots of alignment faults in
their gconv code, which if not fixed up, results in segfaults during
boot.  This can prevent systems booting properly.

There is no clear hard-configurable default for this; the desired
default depends on the nature of the userspace which is going to be
booted.

So, provide a way for the alignment fault handler to be configured via
the kernel command line.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      d944d549
  15. 20 2月, 2010 5 次提交
    • R
      ARM: Update mach-types · 0fa11802
      由 Russell King 提交于 
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      0fa11802
    • A
      ARM: 5950/1: ARM: Fix build error for arm1026ej-s processor · 1c8e170a
      由 Abdoulaye Walsimou Gaye 提交于 
      This patch fix the below build error for arm1026ej-s processor (IntegratorCP/arm1026ej-s board).
  CC      init/main.o
In file included from include/linux/highmem.h:8,
                 from include/linux/pagemap.h:10,
                 from include/linux/mempolicy.h:62,
                 from init/main.c:52:
arch/arm/include/asm/cacheflush.h:134:2: error: #error Unknown cache maintainence model
make[1]: *** [init/main.o] Erreur 1
make: *** [init] Erreur 2
Signed-off-by: NAbdoulaye Walsimou Gaye <walsimou@walsimou.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      1c8e170a
    • D
      sparc64: Fix sun4u execute bit check in TSB I-TLB load. · 1f474646
      由 David S. Miller 提交于 
      Thanks to testcase and report from Brad Spengler:

--------------------
#include <stdio.h>

typedef int (* _wee)(void);

int main(void)
{
        char buf[8] = { '\x81', '\xc7', '\xe0', '\x08', '\x81', '\xe8',
                        '\x00', '\x00' };
        _wee wee;
        printf("%p\n", &buf);
        wee = (_wee)&buf;
        wee();

        return 0;
}
--------------------

TSB I-tlb load code tries to use andcc to check the _PAGE_EXEC_4U bit,
but that's bit 12 so it gets sign extended all the way up to bit 63
and the test nearly always passes as a result.

Use sethi to fix the bug.
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1f474646
    • F
      hw-breakpoint: Keep track of dr7 local enable bits · 326264a0
      由 Frederic Weisbecker 提交于 
      When the user enables breakpoints through dr7, he can choose
between "local" or "global" enable bits but given how linux is
implemented, both have the same effect.

That said we don't keep track how the user enabled the breakpoints
so when the user requests the dr7 value, we only translate the
"enabled" status using the global enabled bits. It means that if
the user enabled a breakpoint using the local enabled bit, reading
back dr7 will set the global bit and clear the local one.

Apps like Wine expect a full dr7 POKEUSER/PEEKUSER match for emulated
softwares that implement old reverse engineering protection schemes.

We fix that by keeping track of the whole dr7 value given by the user
in the thread structure to drop this bug. We'll think about
something more proper later.

This fixes a 2.6.32 - 2.6.33-x ptrace regression.
Reported-and-tested-by: NMichael Stefaniuc <mstefani@redhat.com>
Signed-off-by: NFrederic Weisbecker <fweisbec@gmail.com>
Acked-by: NK.Prasad <prasad@linux.vnet.ibm.com>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Maneesh Soni <maneesh@linux.vnet.ibm.com>
Cc: Alexandre Julliard <julliard@winehq.org>
Cc: Rafael J. Wysocki <rjw@sisk.pl>
Cc: Maciej Rutecki <maciej.rutecki@gmail.com>
      326264a0
    • F
      hw-breakpoints: Accept breakpoints on NULL address · 84d71092
      由 Frederic Weisbecker 提交于 
      Before we had a generic breakpoint API, ptrace was accepting
breakpoints on NULL address in x86. The new API refuse them,
without given strong reasons. We need to follow the previous
behaviour as some userspace apps like Wine need such NULL
breakpoints to ensure old emulated software protections
are still working.

This fixes a 2.6.32 - 2.6.33-x ptrace regression.
Reported-and-tested-by: NMichael Stefaniuc <mstefani@redhat.com>
Signed-off-by: NFrederic Weisbecker <fweisbec@gmail.com>
Acked-by: NK.Prasad <prasad@linux.vnet.ibm.com>
Acked-by: NRoland McGrath <roland@redhat.com>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Maneesh Soni <maneesh@linux.vnet.ibm.com>
Cc: Alexandre Julliard <julliard@winehq.org>
Cc: Rafael J. Wysocki <rjw@sisk.pl>
Cc: Maciej Rutecki <maciej.rutecki@gmail.com>
      84d71092