The functions exynos4_clk_init and exynos4_clk_register_fixed_ext
are applicable only on Exynos4 non-dt platforms. But when building
Exynos5 platforms without including Exynos4 platforms, the following
errors show up.

arch/arm/mach-exynos/built-in.o: In function `exynos_init_time':
arch/arm/mach-exynos/common.c:446: undefined reference to `exynos4_clk_init'
arch/arm/mach-exynos/common.c:447: undefined reference to `exynos4_clk_register_fixed_ext'

Fix this compilation errors by marking these calls as Exynos4 specific.
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

With support for device tree based clock lookup now available, remove
the auxdata table from exynos4/5 dt-enabled machine file.
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The clock speed of xxti and xusbxti clocks depends on the oscillator
used on the board to generate these clocks. For non-dt platforms,
allow the board support for those platforms to set the clock frequency
of xxti and xusbxti clocks.
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Since the clock initialization should be completed prior to the mct
timer initialization, create a new function 'exynos_init_time' that
first sets up the clock and then invokes the timer initialization
function. The 'init_time' callback in the board files are updated to
invoke this new wrapper function.
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Remove Samsung specific clock support in Exynos4/5 and migrate to
use common clock framework.
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Tested-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Move the multi core timer (mct) driver to from mach-exynos
to drivers/clocksource and update the Kconfig and makefiles.

Cc: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

With device tree support enabled for MCT controller, the
staticio-remapping of the MCT controller address space is
removed for Exynos5 platforms (which supports only device
tree based boot).

Cc: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add entries to __clksrc_of_table so that Exynos MCT controller is
discoverable using call to clocksource_of_init. With this change,
it would be appropriate to rename the function 'exynos4_timer_init'
as 'mct_init' since it aptly describes this function. Additionally,
the 'init_time' callback of all machine descriptors for exynos
platforms that were previously set to 'exynos4_timer_init' are now
set to either 'mct_init' or 'clocksource_of_init'.

Cc: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Allow the MCT controller base address and interrupts to be
obtained from device tree and remove unused static definitions
of these. The non-dt support for Exynos5250 is removed but
retained for Exynos4210 based platforms.

Cc: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Instead of using soc_is_xxx macro at more than one place in
the MCT controller driver to decide the MCT interrpt number
to be setup, populate a table of known MCT global and local
timer interrupts and use the values in table to setup the MCT
interrupts.

This also helps in adding device tree support for MCT controller
driver by allowing the driver to retrieve interrupt numbers from
device tree and populating them into this table, thereby supporting
both legacy and dt functionality to co-exist.

Cc: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

All the MCT register read/writes use a fixed remapped address
S5P_VA_SYSTIMER.  With device tree support for MCT controller,
it is possible to remove the static remap of the MCT controller
address space and do the remap during the initialization of the
MCT controller with the physical address obtained from the device
tree.

So in preparation of adding device tree support for MCT controller,
add a new register base address variable that will hold the remapped
MCT controller base address and convert all MCT register read/writes
to use this new variable as the base address instead of the fixed
S5P_VA_SYSTIMER.

While at it, the MCT register offset and bit mask definitions are
moved into the MCT controller driver file since there are no other
consumers of these definitions.

Cc: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds device tree nodes for MFC and G-scaler power
domains of exynos5250.It binds these power-domain nodes to repsective
device tree nodes

It also adds support to enable PM generic domains for exynos5250.
Signed-off-by: NPrasanna Kumar <prasanna.ps@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Use AUXDATA to set the device names for DP controller instance
discovered from device tree.
Signed-off-by: NAjay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Signed-off-by: NNaour Romain <romain.naour@openwide.fr>
Reviewed-by: NTomasz Figa <tomasz.figa@gmail.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Exynos boot is broken with commit 0529e315 (ARM: use common irqchip_init
for GIC init). This commit split the irqchip initialization into 2 calls
to of_irq_init. This does not work because of_irq_init requires interrupt
parents to be in the match list.

Rather than reverting exynos changes, make it do the proper thing by using
IRQCHIP_DECLARE. This requires moving the combiner code to drivers/irqchip.
Reported-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-samsung-soc@vger.kernel.org
Signed-off-by: NOlof Johansson <olof@lixom.net>

Newer Exynos4 SoC are equipped with a local camera ISP that
controls external raw image sensor directly. Such sensors
can be connected through FIMC-LITEn (and MIPI-CSISn) IPs to
the ISP, which then feeds image data to the FIMCn IP. Thus
there can be two busses associated with an image source
(sensor). Rename struct s5p_fimc_isp_info describing external
image sensor (video decoder) to struct fimc_source_info to
avoid confusion. bus_type is split into fimc_bus_type and
sensor_bus_type. The bus type enumeration is extended to
include both FIMC Writeback input types.
The bus_type enumeration and the data structure name in the
board files are modified according to the above changes.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>

Since pinctrl-exynos can support exynos4 and exynos5 so changed
the option name to PINCTRL_EXYNOS for more clarity.

Cc: Thomas Abraham <Thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

As per the Exynos5250 User Manual:
When there are pending interrupt events, WFI/WFE instruction are
ignored. To cancel the power-down sequence follow these steps:
1) Disable system power-down using CENTRAL_SEQ_CONFIGURATION register
2) Clear WAKEUP_STAT register
3) Enable interrupt service routine for CPU

Code for early wakeup for exynos already exists. Remove the panic
on suspend failure, clear the wakeup state register and return 1
from cpu_suspend to indicate a failed suspend (to a user daemon).

Older Samsung SoCs have similar panics and I have removed them all.
Haven't touched the S3C2410 sleep code.
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add AUXDATA entries for i2s controller driver so as to set the device
name for clock lookups
Signed-off-by: NPadmavathi Venna <padma.v@samsung.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

The soft-reset control register is located in the XMU controller space.
Map this controller space before writing to the soft-reset controller
register.
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NGirish K S <ks.giri@samsung.com>
Signed-off-by: NKukjin <kgene.kim@samsung.com>

Fix the incorrect compatible property value of pinctrl for EXYNOS4 SoCs.

Cc: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Since pinctrl-exynos can support exynos4 and exynos5 so changed
the option name to PINCTRL_EXYNOS for more clarity.

Cc: Thomas Abraham <Thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The clockevent core is able to figure out the best mult and shift,
calculate min_delta_ns and max_delta_ns, with the necessary info passed
into clockevents_config_and_register().  Use this combined configure
and register function where possible to make the codes less error prone
and gain some positive diff stat.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Reviewed-by: NAnton Vorontsov <cbouatmailru@gmail.com>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Tested-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NEric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: David Brown <davidb@codeaurora.org>
Tested-by: NTony Lindgren <tony@atomide.com>
Acked-by: NBarry Song <baohua.song@csr.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NTony Prisk <linux@prisktech.co.nz>
Cc: Lennert Buytenhek <buytenh@wantstofly.org>
Cc: Wan ZongShun <mcuos.com@gmail.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Reviewed-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Now that we have GIC moved to drivers/irqchip and all GIC DT init for
platforms using irqchip_init, move gic.h and update the remaining
includes.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Anton Vorontsov <avorontsov@mvista.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Samuel Ortiz <sameo@linux.intel.com>

Convert all GIC DT initialization over to use common irqchip_init
function.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>

Now that the GIC initialization sets up the handle_arch_irq pointer, we
can remove it for all machines and make it static.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Anton Vorontsov <avorontsov@mvista.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>
Acked-by: NArnd Bergmann <arnd@arndb.de>

This removes System MMU initialization from arch/arm/mach-exynos/
to move them to DT and the exynos-iommu driver except gating clock
definitions.
Signed-off-by: NKyongHo Cho <pullip.cho@samsung.com>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NJoerg Roedel <joro@8bytes.org>

Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

In preparation of moving gic code to drivers/irqchip, remove the direct
platform dependencies on gic_raise_softirq. Move the setup of
smp_cross_call into the gic code and use arch_send_wakeup_ipi_mask
function to trigger wake-up IPIs.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>

Since exynos5440 can support only common clk stuff, so this
patch skips legacy exynos5 clock initialization.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch removes following warning in kernel boot log,
Because EXYNOS5440 can support only Pinctrl not GPIO.

WARNING: at drivers/gpio/gpio-samsung.c:3102 samsung_gpiolib_init+0x68/0x8c()
Unknown SoC in gpio-samsung, no GPIOs added

Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Now that the only field in struct sys_timer is .init, delete the struct,
and replace the machine descriptor .timer field with the initialization
function itself.

This will enable moving timer drivers into drivers/clocksource without
having to place a public prototype of each struct sys_timer object into
include/linux; the intent is to create a single of_clocksource_init()
function that determines which timer driver to initialize by scanning
the device dtree, much like the proposed irqchip_init() at:
http://www.spinics.net/lists/arm-kernel/msg203686.html

Includes mach-omap2 fixes from Igor Grinberg.
Tested-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Signed-off-by: NJonghwan Choi <jhbird.choi@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The variable 'max_support_idx, min_support_idx, pm_lock_idx"
are never used, so remove the unused variable.
Signed-off-by: NJonghwan Choi <jhbird.choi@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

I2S controller has an internal mux for RCLK source clks. The list
of source clk names were passed through platform data in non-dt case.
The variable holding the list of RCLK source clk names is not
required, as the list of clks need to be registered with clkdev
using generic connection id. This is required as part of adding DT
support for I2S controller driver.
Signed-off-by: NPadmavathi Venna <padma.v@samsung.com>
Acked-by: NSangbeom Kim <sbkim73@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Replace clock instance name of MSHC controller for BIC and CIU of Exynos4412.
Signed-off-by: NDongjin Kim <tobetter@gmail.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

When DRM support for Samsung SoC and Samsung S3C framebuffer support
are selected, the kernel crashes as it does not get the required
platform data. Change the compile macro to CONFIG_DRM_EXYNOS_FIMD
to fix this.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>