Implement generic time support for MN10300.
Signed-off-by: NMark Salter <msalter@redhat.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Use an ELF HWCAP flag to indicate to the process that the CPU provides LL/SC
equivalent atomic operations unit support in addition to BSET/BCLR.
Signed-off-by: NMark Salter <msalter@redhat.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

The AM34 processor has an atomic operation that's the equivalent of LL/SC on
other architectures.  However, rather than being done through a pair of
instructions, it's driven by writing to a pair of memory-mapped CPU control
registers.

One set of these registers (AARU/ADRU/ASRU) is available for use by userspace,
but for userspace to access them a PTE must be set up to cover the region.
This is done by dedicating the first vmalloc region page to this purpose,
setting the permissions on its PTE such that userspace can access the page.

glibc is hardcoded to expect the registers to be there.

The way atomic ops are done through these registers is straightforward:

 (1) Write the address of the word you wish to access into AARU.  This causes
     the CPU to go and fetch that word and load it into ADRU.  The status bits
     are also cleared in ASRU.

 (2) The current data value is read from the ADRU register and modified.

 (3) To alter the data in RAM, the revised data is written back to the ADRU
     register, which causes the CPU to attempt to write it back.

 (4) The ASRU.RW flag (ASRU read watch), ASRU.LW flag (bus lock watch),
     ASRU.IW (interrupt watch) and the ASRU.BW (bus error watch) flags then
     must be checked to confirm that the operation wasn't aborted.  If any of
     the watches have been set to true, the operation was aborted.
Signed-off-by: NMark Salter <msalter@redhat.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for
MN10300.  Also implement support for the MN2WS0060 processor and the ASB2364
evaluation board which are AM34 based.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Delete idle_timestamp from irq_cpustat_t as it's an unread relic.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Make the settings of interrupt priorities used by various services configurable
at run time.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Optimise do_csum() to gang up the loads so they're less likely to get
interruptions between.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Implement atomic ops using the atomic ops unit available in the AM34 CPU.  This
allows the equivalent of the LL/SC instructions to be found on other CPUs.
Signed-off-by: NMark Salter <msalter@redhat.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Make the FPU operate in non-lazy mode under SMP so that when the process that
is currently using the FPU migrates to a different CPU, we don't have to ping
its previous CPU to flush the FPU context.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Implement global TLB flushing for MN10300.  This will be used by the AM34 which
is SMP capable.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control as the bits
are a more suitable layout.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Make controllable the use of the PIDR register to mark TLB entries as belonging
to particular processes.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Rename __flush_tlb*() to local_flush_tlb*() as it's more appropriate, and ready
to differentiate local from global TLB flushes when SMP is introduced.

Whilst we're at it, get rid of __flush_tlb_global() and make
local_flush_tlb_page() take an mm_struct pointer rather than VMA pointer.
Signed-off-by: NDavid Howells <dhowells@redhat.com>

An AM34 erratum requires MMUCTR read and write on entry to certain exceptions,
prior to EPSW.NMID being cleared to allow NMIs to happen.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Make the boot wrapper able to use writeback caching, including flushing the
cache before jumping to the main kernel.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Implement SMP global cache flushing for MN10300.  This will be used by the AM34
which is SMP capable.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

The AM34 core is able to do cache snooping, and so can skip some of the cache
flushing.
Signed-off-by: NDavid Howells <dhowells@redhat.com>

The AM34 CPU core provides an automated way of purging the cache rather than
manually iterating over all the tags in the cache.  Make it possible to use
these.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Differentiate local cache flushing from global cache flushing so that they can
be done differently on SMP systems.

Rename the cache functions from:

	mn10300_[id]cache_*()

to:

	mn10300_[id]_localcache_*()

and on a UP system, assign the global labels to the local labels.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

The functions that perform cache flushing should take addresses of unsigned
long type, not unsigned int.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

The current cache flush and invalidate routines operate by controlling the
cache tag registers.  Rename the files and add config items to select them.

This makes it easier to support the use of other cache flush methods instead,
such as the use of AM34's area purge registers, if available.
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Reorder asm/cacheflush.h to put arch primitives first, before the main
functions so that the main functions can be inline asm rather than #defines
when non-trivial.
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Provide a MN10300_CACHE_ENABLED config option as inverted logic of
MN10300_CACHE_DISABLED to make things simpler.
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Split the cache bits out of arch/mn10300/Kconfig as they're quite complex.
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Remove the monitor trap function and the set_jtag_stub function as they're not
really necessary.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Add CPU register declarations for the AM34 subarch.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Don't hard code the cacheline size in the cache control register definitions.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Move the DMA engine control register definitions to the MN103E010 processor
directory so that the MN2WS0050 processor can have its own.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Differentiate AM33_2 and AM33_3 CPU cores in configuration.  The MN103E010
processor contains an AM33_2 core.

Whilst we're at it, prepare for AM34-based stuff by declaring AM34_2 too.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

The local_irq_disable() function and co. merely raise the interrupt mask on the
MN10300 arch to exclude normal interrupts.  This still lets other, higher
priority maskable interrupts through, such as are used to service gdbstub's
serial port and the MN10300 on-chip serial port virtual FIFOs.

Provide functions to allow the maskable interrupts to be fully disabled, which
will exclude those interrupts.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Add reads[bwl]() and writes[bwl]() for MN10300.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Don't cast away the volatile in test_bit()'s parameter when we change its type
from const volatile void * so that we can dereference it.
Signed-off-by: NAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: NKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Typedef the pointer to the function to be called by smp_call_function() and
friends:

	typedef void (*smp_call_func_t)(void *info);

as it is used in a fair number of places.
Signed-off-by: NDavid Howells <dhowells@redhat.com>
cc: linux-arch@vger.kernel.org

Prevent cnt32_to_63() from being preempted in sched_clock() because it may
read its internal counter, get preempted, get delayed for more than the half
period of the 'TSC' and then write the internal counter, thus corrupting it.

Whilst some callers of sched_clock() have interrupts disabled or hold
spinlocks, not all do, and so preemption must be held here.

Note that sched_clock() is called from lockdep, but that shouldn't be a problem
because although preempt_disable() calls into lockdep, lockdep has a recursion
counter to deal with this.
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Instead of open-coding pci_find_parent_resource and request_resource,
just call pci_claim_resource.
Signed-off-by: NMatthew Wilcox <willy@linux.intel.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Change the index to unsigned long in all bitops for [mn10300]
Signed-off-by: NJustin Chen <justin.chen@hp.com>
Reviewed-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Signed-off-by: NStoyan Gaydarov <stoyboyker@gmail.com>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Partially revert patch:

	commit 3234282f
	Author: Jan Beulich <JBeulich@novell.com>
	Date:   Tue Oct 19 14:52:26 2010 +0100
	x86, asm: Fix CFI macro invocations to deal with shortcomings in gas

This breaks MN10300 arch as this changes many instances of instructions
similar to the following:

	MOV	number,D0

which represents an immediate value load into:

	MOV	(number),D0

which the assembler then interprets as a load from absolute address.

arch/mn10300/kernel/entry.S:64: Error: Invalid opcode/operands
arch/mn10300/kernel/entry.S:65: Error: junk at end of line, first unrecognized character is `0'
arch/mn10300/kernel/entry.S:74: Error: Invalid opcode/operands
arch/mn10300/kernel/entry.S:74: Error: junk at end of line, first unrecognized character is `1'
arch/mn10300/kernel/entry.S:75: Error: Invalid opcode/operands
arch/mn10300/kernel/entry.S:76: Error: junk at end of line, first unrecognized character is `0'

cc: Jan Beulich <jbeulich@novell.com>
cc: Alexander van Heukelum <heukelum@fastmail.fm>
cc: H. Peter Anvin <hpa@linux.intel.com>
cc: Ingo Molnar <mingo@elte.hu>
Signed-off-by: NDavid Howells <dhowells@redhat.com>

usbfs_get_inode() is something completely different...

Bogosity introduced by commit 85fe4025 ("fs: do not assign default
i_ino in new_inode").
Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
Cc: Christoph Hellwig <hch@lst.de>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

* 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (476 commits)
  vmwgfx: Implement a proper GMR eviction mechanism
  drm/radeon/kms: fix r6xx/7xx 1D tiling CS checker v2
  drm/radeon/kms: properly compute group_size on 6xx/7xx
  drm/radeon/kms: fix 2D tile height alignment in the r600 CS checker
  drm/radeon/kms/evergreen: set the clear state to the blit state
  drm/radeon/kms: don't poll dac load detect.
  gpu: Add Intel GMA500(Poulsbo) Stub Driver
  drm/radeon/kms: MC vram map needs to be >= pci aperture size
  drm/radeon/kms: implement display watermark support for evergreen
  drm/radeon/kms/evergreen: add some additional safe regs v2
  drm/radeon/r600: fix tiling issues in CS checker.
  drm/i915: Move gpu_write_list to per-ring
  drm/i915: Invalidate the to-ring, flush the old-ring when updating domains
  drm/i915/ringbuffer: Write the value passed in to the tail register
  agp/intel: Restore valid PTE bit for Sandybridge after bdd30729
  drm/i915: Fix flushing regression from 9af90d19
  drm/i915/sdvo: Remove unused encoding member
  i915: enable AVI infoframe for intel_hdmi.c [v4]
  drm/i915: Fix current fb blocking for page flip
  drm/i915: IS_IRONLAKE is synonymous with gen == 5
  ...

Fix up conflicts in
 - drivers/gpu/drm/i915/{i915_gem.c, i915/intel_overlay.c}: due to the
   new simplified stack-based kmap_atomic() interface
 - drivers/gpu/drm/vmwgfx/vmwgfx_drv.c: added .llseek entry due to BKL
   removal cleanups.