The periph_clk2_sel mux can be set to pll3, osc/pll1_ref_clk, or osc/
pll2_burn_in_clk. The periph2_clk2_sel mux can be set to pll3 or pll2.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Since commit 657eee7d (media: coda: use genalloc API) the following build
error happens with imx_v4_v5_defconfig:

drivers/built-in.o: In function 'coda_remove':
clk-composite.c:(.text+0x112180): undefined reference to 'gen_pool_free'
drivers/built-in.o: In function 'coda_probe':
clk-composite.c:(.text+0x112310): undefined reference to 'of_get_named_gen_pool'
clk-composite.c:(.text+0x1123f4): undefined reference to 'gen_pool_alloc'
clk-composite.c:(.text+0x11240c): undefined reference to 'gen_pool_virt_to_phys'
clk-composite.c:(.text+0x112458): undefined reference to 'dev_get_gen_pool'

Select GENERIC_ALLOCATOR and get rid of the custom IRAM_ALLOC.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Commit bca7a5a0 (ARM: cpu hotplug: remove majority of cache flushing
from platforms) removes include of <asm/cacheflush.h> and hence
discovers a few indirect inclusion and declaration problems as below.

  CC      arch/arm/mach-imx/hotplug.o
In file included from arch/arm/mach-imx/hotplug.c:16:0:
arch/arm/mach-imx/common.h:100:29: warning: ‘struct pt_regs’ declared inside parameter list [enabled by default]
arch/arm/mach-imx/common.h:100:29: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default]
arch/arm/mach-imx/common.h:101:29: warning: ‘struct pt_regs’ declared inside parameter list [enabled by default]
arch/arm/mach-imx/hotplug.c: In function ‘imx_cpu_die’:
arch/arm/mach-imx/hotplug.c:53:2: error: implicit declaration of function ‘cpu_do_idle’ [-Werror=implicit-function-declaration]
arch/arm/mach-imx/hotplug.c: In function ‘imx_cpu_kill’:
arch/arm/mach-imx/hotplug.c:58:26: error: ‘jiffies’ undeclared (first use in this function)
arch/arm/mach-imx/hotplug.c:58:26: note: each undeclared identifier is reported only once for each function it appears in
arch/arm/mach-imx/hotplug.c:58:2: error: implicit declaration of function ‘msecs_to_jiffies’ [-Werror=implicit-function-declaration]
arch/arm/mach-imx/hotplug.c:61:3: error: implicit declaration of function ‘time_after’ [-Werror=implicit-function-declaration]

Fix them by adding the needed inclusion and declaration.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The ARM CPU suspend function has its own configuration symbol,
which we need to use for conditionalizing any code calling into
it as well.

arch/arm/mach-imx/built-in.o: In function `v7_cpu_resume':
/git/arm-soc/arch/arm/mach-imx/headsmp.S:57: undefined
 reference to `cpu_resume'

Cc: Sascha Hauer <kernel@pengutronix.de>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The new reset controller API is optional, so if that is disabled,
we must not call it from platform code.

arch/arm/mach-imx/built-in.o: In function
 `imx_src_init': /git/arm-soc/arch/arm/mach-imx/src.c:144:
	undefined reference to `reset_controller_register'

Cc: Sascha Hauer <kernel@pengutronix.de>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

device_register() returns -ve values for errors, and zero for success.
There's no need to obfuscate the code with IS_ERR_VALUE().
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The code intializes the cpuidle driver at different places.
The cpuidle driver for :
  * imx5 : is in the pm-imx5.c, the init function is in cpuidle.c
  * imx6 : is in cpuidle-imx6q.c, the init function is in cpuidle.c
           and cpuidle-imx6q.c

Instead of having the cpuidle code spread across different files,
let's create a driver for each SoC and use the common register function.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

The en_core_tk_irqen flag is set in all the cpuidle driver which
means it is not necessary to specify this flag.

Remove the flag and the code related to it.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Kevin Hilman <khilman@linaro.org>  # for mach-omap2/*
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

Remove the majority of cache flushing calls from the individual platform
files.  This is now handled by the core code.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Use imx_clk_mux_flags to set the appropriate flags for the TVE
selector clock. This is needed so tve_clk rate changes can propagate
up to pll4_sw.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Remove the tve_di clock from the CCM clock tree. It will be provided
by the Television Encoder driver, as this clock is an output signal
of the TVE module.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This is needed so the Television Encoder driver can set the rate
on tve_clk and have it propagated up to pll4_sw.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

On i.MX53, there is only tve_ext_sel.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This adds the clock gates and the binding documentation
for PATA and SRTC.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The i.MX6 Quad can be fused as i.MX6 Dual chip, and similarly i.MX6
DualLite can be fused as i.MX6 Solo.  The actual number of available
cores can be found out from SCU.

Since we do not reflect the fusing thing in device tree, the function
arm_dt_init_cpu_maps() will always call set_cpu_possible(true) for 4
cores on i.MX6 Quad/Dual and 2 cores for i.MX6 DualLite/Solo.  This
causes failures when kernel tries to bring those unavailable cores
online.  For example, the following failure message will be seen when
booting an i.MX6 Solo chip.

  CPU1: failed to come online

Though kernel will still boot fine, the message is somehow annoying.
Let's get rid of it by calling set_cpu_possible(false) on those
unavailable cores.

While at it, the set_cpu_possible(true) for available cores is removed,
since it's already been done in arm_dt_init_cpu_maps().
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The i.MX6 DualLite/Solo is another i.MX6 family SoC, which is highly
compatible with i.MX6 Quad/Dual.  And that's why we choose to support
it using imx6q code with cpu_is_imx6dl() check when necessary.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

mxc_device_init() is mandatory for mxc_aips and mxc_ahb bus registration, needed
as parents, at least, for gpio and dma.
Signed-off-by: NGwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

These two clocks connect to external pins and can be muxed to
various internal clocks.
They are typically used either for debugging or to provide
clocks to external chips (eg audio codecs).

Currently only the selectable clocks that already exist in the clock tree
have been added.
Signed-off-by: NMartin Fuzzey <mfuzzey@parkeon.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The SRC has auto-deasserting reset bits that control reset lines to
the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset
controller that can be controlled by those devices using the
reset controller API.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NPavel Machek <pavel@ucw.cz>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Function imx_anatop_get_digprog() that reads register ANADIG_DIGPROG is
called to identify silicon version.  Users might query silicon version
earlier than regmap subsystem is ready.  For example, imx6q clock driver
query revision in mx6q_clocks_init(), where regmap is not initialized
yet.

Change imx_anatop_get_digprog() to map anatop block and read
ANADIG_DIGPROG in the native way, so that the function can work at very
early stage.

While at it, let's move imx_print_silicon_rev() back to
imx6q_timer_init() to have the message show up a little earlier.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

On i.MX6q revision 1.1 and later, set the video PLL as parent for
the LDB clock branch. On revision 1.0, the video PLL is useless
due to missing dividers, so keep the default parent (mmdc_ch1_axi).
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Query silicon revision to determine clock tree and add post
dividers for newer revisions.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The default is for dividers to set CLK_SET_PARENT_RATE and for muxes to
not set that flag. In the LDB clock tree, we need the opposite, so add
functions to create divider and mux clocks with configurable flags.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

So it can be used in clk-imx6q.c for revision dependent clock tree setup.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

There are some config options not selected by imx27 and imx5 that are
necessary to use the cpufreq-cpu0 driver.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch adds the missing GPU2D and GPU3D mux and gate clocks,
and the graphics arbiter gate clock.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Fix the following sparse warnings:

arch/arm/mach-imx/anatop.c:56:6: warning: symbol 'imx_anatop_pre_suspend' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:62:6: warning: symbol 'imx_anatop_post_resume' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:68:6: warning: symbol 'imx_anatop_usb_chrg_detect_disable' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:78:5: warning: symbol 'imx_anatop_get_digprog' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:86:13: warning: symbol 'imx_anatop_init' was not declared. Should it be static?
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

RBC is to control whether some ANATOP sub modules
can enter lpm mode when SOC is into STOP mode, if
RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP
will have below behaviors:

1. Digital LDOs(CORE, SOC and PU) are bypassed;
2. Analog LDOs(1P1, 2P5, 3P0) are disabled;

As the 2P5 is necessary for DRAM IO pre-drive in
STOP mode, so we need to enable weak 2P5 in STOP
mode when 2P5 LDO is disabled.

For RBC settings, there are some rules as below
due to hardware design:

1. All interrupts must be masked during operating
   RBC registers;
2. At least 2 CKIL(32K) cycles is needed after the
   RBC setting is changed.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Enable periphery charge pump for well biasing
at suspend to reduce periphery leakage.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Anatop module have sereval configurations for user
to reduce the power consumption in suspend, provide
suspend/resume interface for further use and enable
fet_odrive to reduce CORE LDO leakage during suspend.

As we have a common anatop file, remove all the operations
of anatop module in other files, use anatop interfaces to
do that.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The TWD and SCU configs are selected by default as long as
MSM_SCORPIONMP is false and/or MCT is false. Implementing the
logic this way certainly saves lines in the Kconfig but it
precludes those machines which select MSM_SCORPIONMP or MCT from
participating in the single zImage effort because when those
machines are combined with other SMP capable machines the TWD and
SCU are no longer selected by default.

Push the select out to the machine entries so that we can compile
these machines together and still select the appropriate configs.

Cc: Barry Song <baohua.song@csr.com>
Acked-by: NDavid Brown <davidb@codeaurora.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: NPawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: NSimon Horman <horms@verge.net.au>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tony Lindgren <tony@atomide.com>
Acked-by: NViresh Kumar <viresh.linux@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus
the IPU2 reset line and multi core CPU reset/enable bits.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NPavel Machek <pavel@ucw.cz>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add cpufreq-cpu0 platform device for imx5 DT init and register the clock
for imx5.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Adds cpufreq-cpu0 platform device for imx27 DT init and adds a clock
registration for cpufreq-cpu0 device.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Similarly as it was done for mx6q, use a DT lookup in order to make maintainance
task for the clock devices easier.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Tested-by: NMarkus Pargmann <mpa@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This removes the unused Kconfig options ARCH_MX5, ARCH_MX51,
ARCH_MX53 and MACH_MX21.
Signed-off-by: NPaul Bolle <pebolle@tiscali.nl>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>