This patch updates device's probing, removal and irq handling in order to
register it as pinctrl device. Pin control data is matched by ACPI UID,
since it is passed along as driver data in acpi_device_id structure.
Signed-off-by: NCristina Ciocan <cristina.ciocan@intel.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch updates the irq chip implementation in order
to interact with the pin control chip model: the chip
contains reference to SOC data and pin/group/community
information is retrieved through the SOC reference.
Signed-off-by: NCristina Ciocan <cristina.ciocan@intel.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch updates the gpio chip implementation in order
to interact with the pin control model: the chip contains
reference to SOC data and pin/group/community information
is retrieved through the SOC reference.
Signed-off-by: NCristina Ciocan <cristina.ciocan@intel.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add implementation for:
- pin control, group information retrieval: count, name and pins
- pin muxing:
  - function information (count, name and groups)
  - mux setting
  - gpio control (enable, disable, set direction)
- pin configuration:
  - pull disable
  - pull up/down and pull strength
  - debounce
  - any other option is treated as not supported.
Signed-off-by: NCristina Ciocan <cristina.ciocan@intel.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In order to implement pin control for Baytrail, we need data
structures in which to store and pass along pin, group, function,
community and SOC data information.

Baytrail has 3 GPIO controllers. Add SCORE, NCORE and SUS
controller data:
- pins (for all controllers),
- pad map for pins (for all controllers; we need this since pads
  are not ordered),
- groups (for SCORE and SUS controllers),
- functions (for SCORE and SUS controllers),
- communities (for all controllers),
- soc specific data gathering all of the above and the ACPI UID
  (for all controllers)

This information is useful for pin control functionality.
NCORE data is lighter than the other two controllers' due to
lack of pin documentation in the public datasheet.

Datasheet:
http://www.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e3800-family-datasheet.htmlSigned-off-by: NCristina Ciocan <cristina.ciocan@intel.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map, since
it does not depend on device tree despite the current name. This
will enforce a consistent naming in pinctr-utils.c and will make
it clear it can be called from outside device tree (e.g. from
ACPI handling code).
Signed-off-by: NIrina Tirdea <irina.tirdea@intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Implement gpio_chip's get_direction() callback, that lets other
drivers get particular GPIOs direction using gpiod_get_direction().
Signed-off-by: NStefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: NEric Anholt <eric@anholt.net>
Reviewed-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add device HID AMDI0030 to match the AMD ACPI Vendor ID (AMDI) as
registered in http://www.uefi.org/acpi_id_list, and the GPIO controller
on future AMD paltform will use the HID instead of AMD0030.
Signed-off-by: NWang Hongcheng <annie.wang@amd.com>
Acked-by: NKen Xue <ken.Xue@amd.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The new helper returns index of the mathing string in an array.  We
would use it here.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The single pinmux controller can be cascaded to the other interrupt
controllers. Hence when propagating wake-up settings to its parent
interrupt controller, there's possiblity of detecting possible recursive
locking and getting lockdep warning.

This patch avoids this false positive by using a separate lockdep class
for this single pinctrl interrupts.

Cc: linux-gpio@vger.kernel.org
Suggested-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Reviewed-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Based on the Allwinner A64 user manual and on the previous sunxi
pinctrl drivers this introduces the pin multiplex assignments for
the ARMv8 Allwinner A64 SoC.
Port A is apparently used for the fixed function DRAM controller, so
the ports start at B here (the manual mentions "n from 1 to 7", so
not starting at 0).
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In the Amlogic Meson8 / Meson8b platforms we have two different buses:
cbus and aobus, corresponding to 2 different power domains (regular and
always-on). On each bus a different set of registers is mapped to manage
muxes, GPIOs and in general to control a clear subset of the pins.

Considering this architecture, having two different pinctrl devices, one
for each bus / power domain, makes much more sense than just having one
single device.

Right now we have one single pin controller driver that uses two
different domains (represented by 'gpio' and 'gpio-ao' sub-nodes in the
DTS) to manage the set of registers on the two buses. This dual-domain
configuration is hardcoded into the driver that strictly requires one
domain for each bus in the same pin controller device.

With this patch we refactor the driver to allow splitting the driver in
two parts. This change is needed to have a proper description of the HW
in the device-tree where we want to introduce aobus and cbus.
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Separate functions for pins controlled by different pin controllers.
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The at91-pio4 pinctrl driver uses SET_SYSTEM_SLEEP_PM_OPS() to
conditionally set the correct suspend/resume options, but they
become unused when CONFIG_PM is disabled:

drivers/pinctrl/pinctrl-at91-pio4.c:827:12: error: 'atmel_pctrl_suspend' defined but not used [-Werror=unused-function]
drivers/pinctrl/pinctrl-at91-pio4.c:847:12: error: 'atmel_pctrl_resume' defined but not used [-Werror=unused-function]

This adds __maybe_unused annotations so the compiler knows
it can silently drop them instead of warning.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This change will also make Coverity happy by avoiding a theoretical NULL
pointer dereference; yet another reason is to use the above helper function
to tighten the code and make it more readable.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The current "CONFIG_PINCTRL_UNIPHIER_PH1_*" is too long.  It would
not hurt to drop "PH1_" because "UNIPHIER_" already well specifies
the SoC family.  Also, rename files for consistency.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The Kconfig currently controlling compilation of this code is:

drivers/pinctrl/sunxi/Kconfig:config PINCTRL_SUN9I_A80_R
drivers/pinctrl/sunxi/Kconfig:  def_bool MACH_SUN9I

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: linux-gpio@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The Kconfig currently controlling compilation of this code is:

drivers/pinctrl/stm32/Kconfig:config PINCTRL_STM32F429
drivers/pinctrl/stm32/Kconfig:  bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

Since module_init translates to device_initcall in the non-modular
case, the init ordering remains unchanged with this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.

Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: linux-gpio@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The Kconfig / Makefile currently controlling compilation of this code is:

drivers/pinctrl/sh-pfc/Makefile:obj-$(CONFIG_PINCTRL_SH_PFC)    += sh-pfc.o
drivers/pinctrl/sh-pfc/Makefile:sh-pfc-objs                     = core.o pinctrl.o

drivers/pinctrl/sh-pfc/Kconfig:config PINCTRL_SH_PFC
drivers/pinctrl/sh-pfc/Kconfig: def_bool y

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

Since module_init already wasn't being used in this code, the init
ordering remains unchanged with this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE tag etc. since all that information
was (or is now) contained at the top of the file in the comments.

Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The Kconfig currently controlling compilation of this code is:

drivers/pinctrl/Kconfig:config PINCTRL_MESON
drivers/pinctrl/Kconfig:        bool

...meaning that it currently is not being built as a module by anyone.

Lets remove the couple traces of modularity so that when reading the
driver there is no doubt it is builtin-only.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

We don't replace module.h with init.h since the file already has that.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.

Cc: Beniamino Galvani <b.galvani@gmail.com>
Cc: Carlo Caione <carlo@endlessm.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Antoine Tenart <antoine.tenart@free-electrons.com>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The Kconfig for this driver is currently:

config PINCTRL_MT6397
        bool "Mediatek MT6397 pin control" if COMPILE_TEST && !MFD_MT6397

...meaning that it is currently not being built as a module by anyone.
Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

Since module_init translates to device_initcall in the non-modular
case, the init ordering remains unchanged with this commit.

We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: linux-gpio@vger.kernel.org
Cc: linux-mediatek@lists.infradead.org
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: NHongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This file is not modular, nor is it using modular functions. The
only thing close is the global THIS_MODULE which comes from export.h
so lets replace it appropriately and cut back on the amount of
header stuff we draw in by several thousand lines.

Cc: linux-gpio@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The pxa2xxx fails some automated builds because of unexported
symbols.
Reported-by: Nkbuild test robot <fengguang.wu@intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

While I was testing irq's on the cubietruck I found a couple of
not working irq pins. Further diving into the problem it opened
up a mess called "manual".

This so called manual (A20 user manual v1.3 dated 2014-10-10) says:

Pin overview:
    Page 237:       EINT26 is on mux 5.
    Page 288:       EINT26 is on mux 6.

The manual is so contradicting that further tests had to be made
to see which of the 2 statements where correct.

This patch is based on actual outcome of these tests and not what
the manual says.

Test procedure used:

Connect a 1 pulse per second (GPS) line to the pin.

echo pin### > /sys/class/gpio/export
echo in > /sys/class/gpio/gpio###/direction
echo rising > /sys/class/gpio/gpio###/edge

Check /proc/interrupts if a irq was attached and if irq's where
received.

Hardware used:
Henry Paulissen: Cubietruck
Andere Przywara: BananaPi M1
Tested-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NAndre Przywara <andre.przywara@arm.com>
Signed-off-by: NHenry Paulissen <henry@nitronetworks.nl>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

While I was testing irq's on the cubietruck I found a couple of
not working irq pins. Further diving into the problem it opened
up a mess called "manual".

This so called manual (A20 user manual v1.3 dated 2014-10-10) says:

Pin overview:
    Page 233:       EINT12 is on pin PC19 mux6.
    Page 236:       EINT12 is on pin PH12 mux6.

Now, it is a bit strange to have the same IRQ on 2 different pins,
but I guess this could still be possible hardware wise. But then:

Pin registers:
    Page 253:       EINT12 is *not* on pin PC19.
    Page 281:       EINT12 is on pin PH12.

The manual is so contradicting that further tests had to be made
to see which of the 2 statements where correct.

This patch is based on actual outcome of these tests and not what
the manual says.

Test procedure used:

Connect a 1 pulse per second (GPS) line to the pin.

echo pin### > /sys/class/gpio/export
echo in > /sys/class/gpio/gpio###/direction
echo rising > /sys/class/gpio/gpio###/edge

Check /proc/interrupts if a irq was attached and if irq's where
received.
Signed-off-by: NHenry Paulissen <henry@nitronetworks.nl>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Commit bdb0066d ("mfd: syscon: Decouple syscon interface from platform
devices") added the possibility to register syscon devices without
associated platform device. This also removed regmap debugfs facilities,
which don't work without a device. This patch associates the syscon regmap
that handles the IOMUX controller's general purpose registers with the
pinctrl device so that the GPR registers appear in the regmap debugfs
directory again. For example, on i.MX6Q the GPR registers now can be
read from /sys/kernel/debug/regmap/20e0000.iomuxc-gpr/registers.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The DT bindings for pinctrl-bcm2835 allow both the function and pull
to contain either one entry or one per pin. However, an error in the
DT parsing can cause failures if the number of pulls differs from the
number of functions.

Cc: stable@vger.kernel.org
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NPhil Elwell <phil@raspberrypi.org>
Reviewed-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add support for setting up GPIO pin interrupts in the lpc18xx pinctrl
driver. The LPC18xx SCU contain two registers that sets up the signal
routing to the GPIO pin interrupt (PINT) block. The routing uses the
GPIO namespace and not the pin namespace so a lookup is preformed on
the pin.

Routing configuration is done in the device tree by using the new
nxp,gpio-pin-interrupt property. This property takes single parameter
which sets the PINT hwirq for the GPIO.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

pinctrl_find_gpio_range_from_pin takes the pctldev->mutex but so
does pinconf_pins_show and this will cause a deadlock if
pinctrl_find_gpio_range_from_pin is used in .pin_config_get
callback.

Create a nolock version of pinctrl_find_gpio_range_from_pin to
allow pin to gpio lookup to be used from pinconf_pins_show.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The initialization of ngroups is occurring at the end of the
first iteration of the outer loop, which means that the
assignment  pins[ngroups++] = i is potentially indexing into
a region outside of array pins because ngroups is not initialized.
Instead, initialize ngroups in the inner loop before the first
inner loop iteration.
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Reviewed-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds CANFD[0-1] pinmux support to r8a7795 SoC.
Signed-off-by: NRamesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds CAN[0-1] pinmux support to r8a7795 SoC.
Signed-off-by: NRamesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

GP2[29] muxing is controlled by 2-bit IP6[3:2] field, yet only 3 values
are listed instead of 4...

[Sergei: fixed up the formatting, renamed, added the changelog.]
Signed-off-by: NAndrey Gusakov <andrey.gusakov@cogentembedded.com>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Make use of ARCH_RENESAS in place of ARCH_SHMOBILE.

This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This is set by the device core.

Cc: John Crispin <blogic@openwrt.org>
Reported-by: Nkbuild test robot <fengguang.wu@intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the driver and header files required to make pinctrl work on MediaTek
MT7623.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This makes the driver use the data pointer added to the gpio_chip
to store a pointer to the state container instead of relying on
container_of().

Cc: bcm-kernel-feedback-list@broadcom.com
Cc: Scott Branden <sbranden@broadcom.com>
Cc: Jon Mason <jonmason@broadcom.com>
Acked-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

To use pin as eint, user should make sure that:
1. pin is set to right mode, this is done in .irq_request_resources
implementation already.
2. direction of the pin is input, which should call GPIO API to set
pin to input gpio.
We add what step 2 do to .irq_request_resources so that user doesn't
need call GPIO API any more when pin for eint usage.
Signed-off-by: NBiao Huang <biao.huang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Since input-disable cuts off input signal of gpio, add input-enable
setting in .gpio_request_enable implementation to ensure gpio function well
Signed-off-by: NBiao Huang <biao.huang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the EtherAVB pin groups to the R8A7794 PFC driver.

Based on the patches by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>