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  1. 08 6月, 2012 4 次提交
  3. 01 6月, 2012 1 次提交
    • S
      x86: Allow nesting of the debug stack IDT setting · f8988175
      由 Steven Rostedt 提交于 
      When the NMI handler runs, it checks if it preempted a debug handler
and if that handler is using the debug stack. If it is, it changes the
IDT table not to update the stack, otherwise it will reset the debug
stack and corrupt the debug handler it preempted.

Now that ftrace uses breakpoints to change functions from nops to
callers, many more places may hit a breakpoint. Unfortunately this
includes some of the calls that lockdep performs. Which causes issues
with the debug stack. It too needs to change the debug stack before
tracing (if called from the debug handler).

Allow the debug_stack_set_zero() and debug_stack_reset() to be nested
so that the debug handlers can take advantage of them too.

[ Used this_cpu_*() over __get_cpu_var() as suggested by H. Peter Anvin ]
Signed-off-by: NSteven Rostedt <rostedt@goodmis.org>
      f8988175
  5. 31 5月, 2012 2 次提交
  7. 24 5月, 2012 3 次提交
  9. 23 5月, 2012 1 次提交
  11. 18 5月, 2012 1 次提交
  13. 15 5月, 2012 2 次提交
  15. 09 5月, 2012 12 次提交
  17. 07 5月, 2012 1 次提交
  19. 30 4月, 2012 3 次提交
  21. 27 4月, 2012 1 次提交
  23. 26 4月, 2012 2 次提交
  25. 25 4月, 2012 1 次提交
  27. 21 4月, 2012 1 次提交
  29. 20 4月, 2012 2 次提交
    • S
      x86, intel_cacheinfo: Fix error return code in amd_set_l3_disable_slot() · a720b2dd
      由 Srivatsa S. Bhat 提交于 
      If the L3 disable slot is already in use, return -EEXIST instead of
-EINVAL. The caller, store_cache_disable(), checks this return value to
print an appropriate warning.

Also, we want to signal with -EEXIST that the current index we're
disabling has actually been already disabled on the node:

$ echo 12 > /sys/devices/system/cpu/cpu3/cache/index3/cache_disable_0
$ echo 12 > /sys/devices/system/cpu/cpu3/cache/index3/cache_disable_0
-bash: echo: write error: File exists
$ echo 12 > /sys/devices/system/cpu/cpu3/cache/index3/cache_disable_1
-bash: echo: write error: File exists
$ echo 12 > /sys/devices/system/cpu/cpu5/cache/index3/cache_disable_1
-bash: echo: write error: File exists

The old code would say

-bash: echo: write error: Invalid argument

for disable slot 1 when playing the example above with no output in
dmesg, which is clearly misleading.
Reported-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NSrivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/r/20120419070053.GB16645@elgon.mountain
[Boris: add testing for the other index too]
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
      a720b2dd
    • T
      x86/mce: Avoid reading every machine check bank register twice. · 95022b8c
      由 Tony Luck 提交于 
      Reading machine check bank registers is slow. There is a trend of
increasing the number of banks, and the number of cores. The main section
of do_machine_check() is a serialized section where each cpu in turn
checks every bank. Even on a little two socket SandyBridge-EP system
that multiplies out as:

	2 sockets * 8 cores * 2 hyperthreads * 20 banks = 640 MSRs

We already scan the banks in parallel in mce_no_way_out() to see if there
is a fatal error anywhere in the system. If we build a cache of VALID
bits during this scan, we can avoid uselessly re-reading banks that have
no data. Note that this cache is only a hint. If the valid bit is set in a
shared bank, all cpus that share that bank will see it during the parallel
scan, but the first to find it in the sequential scan will (usually) clear
the bank.
Acked-by: NBorislav Petkov <borislav.petkov@amd.com>
Signed-off-by: NTony Luck <tony.luck@intel.com>
      95022b8c
  31. 17 4月, 2012 1 次提交
  33. 16 4月, 2012 2 次提交