- 25 5月, 2015 2 次提交
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由 Kuninori Morimoto 提交于
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: NKeita Kobayashi <keita.kobayashi.ym@renesas.com> Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Andreas Fenkart 提交于
Some drivers schedule automatic hw resets. An example is mwifiex, which schedules a card reset if the command handler between driver and card firmware becomes out of sync Signed-off-by: NAndreas Fenkart <afenkart@gmail.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 18 5月, 2015 1 次提交
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由 Ludovic Desroches 提交于
clkdiv is declared as an u32 but it can be set to a negative value causing a huge divisor value. Change its type to int to avoid this case. Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com> Cc: <stable@vger.kernel.org> # 3.4 and later Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 08 5月, 2015 2 次提交
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由 Zhangfei Gao 提交于
When non-removable is used for emmc, MMC_CAP_NONREMOVABLE should also be checked, otherwise detection fail since present=0 Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Zhangfei Gao 提交于
Set 0 to des1 in 32bit case. Otherwise the random value of des1 will be used in dw_mci_translate_sglist: IDMAC_SET_BUFFER1_SIZE(desc, length) Signed-off-by: NFei Wang <w.f@huawei.com> Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 06 5月, 2015 2 次提交
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由 Chuanxiao Dong 提交于
During kernel boot, it will try to read some logical sectors of each block device node for the possible partition table. But since RPMB partition is special and can not be accessed by normal eMMC read / write CMDs, it will cause below error messages during kernel boot: ... mmc0: Got data interrupt 0x00000002 even though no data operation was in progress. mmcblk0rpmb: error -110 transferring data, sector 0, nr 32, cmd response 0x900, card status 0xb00 mmcblk0rpmb: retrying using single block read mmcblk0rpmb: timed out sending r/w cmd command, card status 0x400900 mmcblk0rpmb: timed out sending r/w cmd command, card status 0x400900 mmcblk0rpmb: timed out sending r/w cmd command, card status 0x400900 mmcblk0rpmb: timed out sending r/w cmd command, card status 0x400900 mmcblk0rpmb: timed out sending r/w cmd command, card status 0x400900 mmcblk0rpmb: timed out sending r/w cmd command, card status 0x400900 end_request: I/O error, dev mmcblk0rpmb, sector 0 Buffer I/O error on device mmcblk0rpmb, logical block 0 end_request: I/O error, dev mmcblk0rpmb, sector 8 Buffer I/O error on device mmcblk0rpmb, logical block 1 end_request: I/O error, dev mmcblk0rpmb, sector 16 Buffer I/O error on device mmcblk0rpmb, logical block 2 end_request: I/O error, dev mmcblk0rpmb, sector 24 Buffer I/O error on device mmcblk0rpmb, logical block 3 ... This patch will discard the access request in eMMC queue if it is RPMB partition access request. By this way, it avoids trigger above error messages. Fixes: 090d25fe ("mmc: core: Expose access to RPMB partition") Signed-off-by: NYunpeng Gao <yunpeng.gao@intel.com> Signed-off-by: NChuanxiao Dong <chuanxiao.dong@intel.com> Tested-by: NMichael Shigorin <mike@altlinux.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Takeshi Kihara 提交于
f9fd54f2 ("mmc: sh_mmcif: Use msecs_to_jiffies() for host->timeout") changed the timeout value from 1000 jiffies to 1s. In the case where HZ is 1000 the values are the same. However, for smaller HZ values the timeout is now smaller, 1s instead of 10s in the case of HZ=100. Since the timeout occurs in spite of a normal data transfer a timeout of 10s seems more appropriate. This restores the previous timeout in the case where HZ=100 and results in an increase over the previous timeout for larger values of HZ. Fixes: f9fd54f2 ("mmc: sh_mmcif: Use msecs_to_jiffies() for host->timeout") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> [horms: rewrote changelog to refer to HZ] Signed-off-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 04 5月, 2015 1 次提交
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由 Grygorii Strashko 提交于
The PM_RESTORE_PREPARE is not handled now in mmc_pm_notify(), as result mmc_rescan() could be scheduled and executed at late hibernation restore stages when MMC device is suspended already - which, in turn, will lead to system crash on TI dra7-evm board: WARNING: CPU: 0 PID: 3188 at drivers/bus/omap_l3_noc.c:148 l3_interrupt_handler+0x258/0x374() 44000000.ocp:L3 Custom Error: MASTER MPU TARGET L4_PER1_P3 (Idle): Data Access in User mode during Functional access Hence, add missed PM_RESTORE_PREPARE PM event in mmc_pm_notify(). Fixes: 4c2ef25f (mmc: fix all hangs related to mmc/sd card...) Signed-off-by: NGrygorii Strashko <Grygorii.Strashko@linaro.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 17 4月, 2015 2 次提交
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由 Ulf Hansson 提交于
This reverts commit 6685ac62 ("mmc: core: Convert mmc_driver to device_driver") The reverted commit went too far in simplifing the device driver parts for mmc. Let's restore the old mmc_driver to enable driver core to sooner or later to remove the ->probe(), ->remove() and ->shutdown() callbacks from the struct device_driver. Note that, the old ->suspend|resume() callbacks in the struct mmc_driver don't need to be restored, since the mmc block layer has converted to the modern system PM ops. Fixes: 6685ac62 ("mmc: core: Convert mmc_driver to device_driver") Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
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由 Javier Martinez Canillas 提交于
If the struct mmc_pwrseq_match .alloc function used to allocate a struct mmc_pwrseq fails, the error is propagated to mmc_of_parse(). But instead of returning the error code in pwrseq, host->pwrseq is returned which will always be 0. So mmc_of_parse() succeeds even if the pwrseq .alloc function failed and host->pwrseq is NULL. This makes the SDIO device to not be powered if the power sequencing .alloc functions wants to be deferred due a missing resource because the mmc controller driver probe did wrongly succeed. Fixes: 0f12a0ce ("mmc: pwrseq: simplify alloc/free hooks") Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 11 4月, 2015 1 次提交
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由 James Bottomley 提交于
The current string_get_size() overflows when the device size goes over 2^64 bytes because the string helper routine computes the suffix from the size in bytes. However, the entirety of Linux thinks in terms of blocks, not bytes, so this will artificially induce an overflow on very large devices. Fix this by making the function string_get_size() take blocks and the block size instead of bytes. This should allow us to keep working until the current SCSI standard overflows. Also fix virtio_blk and mmc (both of which were also artificially multiplying by the block size to pass a byte side to string_get_size()). The mathematics of this is pretty simple: we're taking a product of size in blocks (S) and block size (B) and trying to re-express this in exponential form: S*B = R*N^E (where N, the exponent is either 1000 or 1024) and R < N. Mathematically, S = RS*N^ES and B=RB*N^EB, so if RS*RB < N it's easy to see that S*B = RS*RB*N^(ES+EB). However, if RS*BS > N, we can see that this can be re-expressed as RS*BS = R*N (where R = RS*BS/N < N) so the whole exponent becomes R*N^(ES+EB+1) [jejb: fix incorrect 32 bit do_div spotted by kbuild test robot <fengguang.wu@intel.com>] Acked-by: NUlf Hansson <ulf.hansson@linaro.org> Reviewed-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NJames Bottomley <JBottomley@Odin.com>
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- 10 4月, 2015 6 次提交
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由 Peter Griffin 提交于
Some additional quirks need to be enabled now we support UHS modes. This avoids some spurious warnings like "Got data interrupt 0x00000002 even though no data operation was in progress" Testing on stih410-b2120 board achieves the following speeds with HS200 eMMC card. max-frequency = 200Mhz /dev/mmcblk0p1: Timing buffered disk reads: 270 MB in 3.02 seconds = 89.54 MB/sec max-frequency = 100Mhz root@debian-armhf:~# hdparm -t /dev/mmcblk0p1 /dev/mmcblk0p1: Timing buffered disk reads: 210 MB in 3.00 seconds = 70.00 MB/sec max-frequency = 50Mhz root@debian-armhf:~# hdparm -t /dev/mmcblk0p1 /dev/mmcblk0p1: Timing buffered disk reads: 118 MB in 3.00 seconds = 39.28 MB/sec This is better than the 3.10 kernel which achieves 77.59 MB/sec at 200Mhz clock (same board/soc/eMMC). Signed-off-by: NPeter Griffin <peter.griffin@linaro.org> Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by: NMaxime Coquelin <maxime.coquelin@st.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Peter Griffin 提交于
To allow UHS modes to work properly we need to provide the st specific set_uhs_signaling callback function. This function differs from the generic sdhci_set_uhs_signaling callback in that we need to configure the correct delay depending on the UHS mode, and also set the V18_EN bit. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org> Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by: NMaxime Coquelin <maxime.coquelin@st.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Peter Griffin 提交于
STiH407 family SoC's have glue registers in the flashSS subsystem which are used to configure the Arasan HC. This patch configures these glue registers according to what has been specified in the DT. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org> Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by: NMaxime Coquelin <maxime.coquelin@st.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Peter Griffin 提交于
Due to the tight timing constraints in some UHS modes, it is required to have some delay management in the design. Two types of delay management are supported in the HW: - 1) Static delay management 2) Dynamic delay management NB: The delay management is only there when eMMC interface is selected. 1: Static delay management: is used to provide PVT dependent static delay on the clock/data lines to manage setup/hold requirements of the interface. The maximum delay possible is 3.25ns. These delays are PVT dependent, and thus delay values applied are not accurate and vary across provcess voltage and temperature range. Due to this these delays must not be used on the very time critical paths. 2. Dynamic delay locked loop (DLL): is used to provide dynamic delay management. The advantage of DLL is that it provides accurate & PVT indepedent delay. The DLL is used to provide delay on the loopback clock on "Read Path" to capture read data reliably. On TX path the clock on which output data is transmitted is delayed, resulting in delay of TX data. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org> Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Peter Griffin 提交于
STiH407 family SoC's can have a reset signal for the controller which needs to be managed. Also the eMMC controller has some additional 'top' memory mapped registers which are used to manage the dynamic and static delay required for UHS modes. This patch adds support for creating the mapping, which will be used by subsequent patches. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org> Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by: NMaxime Coquelin <maxime.coquelin@st.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Peter Griffin 提交于
The stih407 family SoC's have additional glue registers in the flashSS which are used to configure the Arasan controller. This patch adds macros for the register offsets and bitfields which will be used by subsequent patches to support stih407 family SoC's. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org> Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by: NMaxime Coquelin <maxime.coquelin@st.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 09 4月, 2015 7 次提交
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由 Fabio Estevam 提交于
Currently it is not possible to use 'mmc-pwrseq-simple' property with this driver because mmc_of_parse() is never called. mmc_of_parse() calls mmc_pwrseq_alloc() that manages MMC power sequence and allows passing GPIOs in the devicetree to properly power/reset the Wifi chipset. When using mmc_of_parse() we no longer need to have custom code to request card-detect and write-protect pins, as this can now be handled by the mmc core. Tested on a imx6sl-warp board where BT/Wifi is functional and also on a imx6q-sabresd. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Doug Anderson 提交于
It is possible for the cmd11 interrupt to fire and delete the cmd11_timer before the cmd11_timer was actually setup. Let's fix this race by adding a few spinlocks. Note that the race wasn't seen in practice without adding some printk statements, but it still seems wise to fix. Fixes: 5c935165 ("mmc: dw_mmc: Add a timeout for sending CMD11") Signed-off-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Doug Anderson 提交于
If we get an unexpected cmd11 timeout we shouldn't actually treat it as a timeout (not that we really expect to get an unexpected cmd11 timeout, but still). Fixes: 5c935165 ("mmc: dw_mmc: Add a timeout for sending CMD11") Reported-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Doug Anderson 提交于
Although the cmd11 interrupt should come within 2ms, that's a very short time. Let's increase the timeout to be really sure that we don't get an accidnetal timeout. One case in particular this is useful is if you've got a serial console and printk in just the right places. Under that scenario I've seen delays of up to 130ms before the interrupt fired. CMD11 is only sent during card insertion, so this extra timeout shouldn't be terrible. Fixes: 5c935165 ("mmc: dw_mmc: Add a timeout for sending CMD11") Signed-off-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Ben Dooks 提交于
The dw_mmc driver changes to make the IO accesors endian agnostic did not take into account the fifo accesses do not need to be swapped. To fix this add a mmci_fifo_read/write wrapper to allow these to be passed through the IO without being swapped. Since these are now specific functions, it would be easier just to store the pointer to the fifo registers in the host block instead of the offset to them. So change the host->data_offset to host->fifo_reg (which also means we catch all the places this is read or written). Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Ben Dooks 提交于
The dw_mmc driver does not take into account the processor may be in big endian when writing the descriptors. Change the descriptors for the 32bit IDMA to use __le32 and ensure they are suitably swapped before writing. Note, this has not been tested as the socfpga driver does not try to use idma. Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Ben Dooks 提交于
The dw_mmc driver does not use endian agnostic IO accessors, so fix the use of __raw reads and writes to be the relaxed versions. This fixes the dw_mmc driver initialisation on Altera socfpga in big endian. Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 08 4月, 2015 2 次提交
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由 Michal Simek 提交于
Also check MMC OF properties. The controller supports MMC too. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Micky Ching 提交于
rts5250 chip failed handle 64 bit ADMA for address below 4G. Add 64 BIT quirks to disable this feature. Signed-off-by: NMicky Ching <micky_ching@realsil.com.cn> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 02 4月, 2015 1 次提交
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由 Hans de Goede 提交于
The eMMC on a tablet I've will stop working / communicating as soon as the kernel executes: mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HPI_MGMT, 1, card->ext_csd.generic_cmd6_time); There seems to be no way to reliable identify eMMC-s which have a broken hpi implementation, but at least for eMMC's which are soldered onto a board we can work around this by specifying that hpi is broken in devicetree. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 01 4月, 2015 1 次提交
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由 Mylene JOSSERAND 提交于
Modify the driver to handle GPIOs using the descriptor API. Signed-off-by: NMylene JOSSERAND <josserand.mylene@gmail.com> Reviewed-by: NAlexandre Courbot <acourbot@nvidia.com> Tested-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 31 3月, 2015 6 次提交
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由 Andreas Fenkart 提交于
Signed-off-by: NAndreas Fenkart <afenkart@gmail.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Andreas Fenkart 提交于
strip the card dectet logic from cover detect isr and vice versa the generic mmc_gpio_cd_irqt isr, uses 200ms on removal/insertion, hence that should be fine here as well Signed-off-by: NAndreas Fenkart <afenkart@gmail.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Doug Anderson 提交于
If dw_mci_init_slot() returns that we got a probe deferral then it may leave slot->mmc as NULL. That will cause dw_mci_enable_cd() to crash when it calls mmc_gpio_get_cd(). Fix this by moving the call of dw_mci_enable_cd() until we're sure that we're good. Note that if we have more than one slot and one defers (but the others don't) things won't work so well. ...but that's not a new thing and everyone has already agreed that multislot support ought to be removed from dw_mmc eventually anyway since it is unused, untested, and you can see several bugs like this by inspecting the code. Fixes: bcafaf5470f0 ("mmc: dw_mmc: Only enable CD after setup and only if needed") Signed-off-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Doug Anderson 提交于
In the Designware databook's description of the "Voltage Switch Normal Scenario" it instructs us to set a timer and fail the voltage change if we don't see the voltage change interrupt within 2ms. Let's implement that. Without implementing this I have often been able to reproduce a hang while trying to send CMD11 on an rk3288-based board while constantly ejecting and inserting UHS cards. Signed-off-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Jaehoon Chung 提交于
Enable card-read-threshold, when eMMC mode is HS400. Refer to f1d2736c (mmc: dw_mmc: control card read threshold) Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Ulf Hansson 提交于
Currently those host drivers which have deployed runtime PM, deals with the runtime PM reference counting entirely by themselves. Since host drivers don't know when the core will send the next request through some of the host_ops callbacks, they need to handle runtime PM get/put between each an every request. In quite many cases this has some negative effects, since it leads to a high frequency of scheduled runtime PM suspend operations. That due to the runtime PM reference count will normally reach zero in-between every request. We can decrease that frequency, by enabling the core to deal with runtime PM reference counting of the host device. Since the core often knows that it will send a seqeunce of requests, it makes sense for it to keep a runtime PM reference count during these periods. More exactly, let's increase the runtime PM reference count by invoking pm_runtime_get_sync() from __mmc_claim_host(). Restore that action by invoking pm_runtime_mark_last_busy() and pm_runtime_put_autosuspend() in mmc_release_host(). In this way a runtime PM reference count will be kept during the complete cycle of a claim -> release host. Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Acked-by: NKonstantin Dorfman <kdorfman@codeaurora.org>
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- 28 3月, 2015 1 次提交
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由 Stephen Boyd 提交于
This driver is orphaned now that mach-msm has been removed. Delete it. Cc: Chris Ball <chris@printf.net> Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Acked-by: NUlf Hansson <ulf.hansson@linaro.org> Signed-off-by: NKumar Gala <galak@codeaurora.org>
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- 27 3月, 2015 3 次提交
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由 Andreas Fenkart 提交于
board-rx51 has no card detect pin in the mmc slot, but can detect that the (cell-phone) cover has been removed and the card is accessible. The semantics between cover/card detect differ, the gpio on the slot informs you after the card has been removed, cover removal does not necessarily mean that the card has been removed. This means different code paths are necessary. To complete this we also want different fields in the platform data for cover and card detect. This separation is not pushed all the way down into struct omap2_hsmmc_info which is used to initialize the platform data. If we did that we had to go over all board files and set the new gpio_cod pin to -EINVAL. If we forget one board or some out-of-tree archicture forgets that the default '0' is used which is a valid pin number. Signed-off-by: NAndreas Fenkart <afenkart@gmail.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 NeilBrown 提交于
These callbacks have been set to deprecated for some time. The last user (omap_hsmmc) has moved away from using them, which thus enables us to completely remove them. Signed-off-by: NNeilBrown <neil@brown.name> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 NeilBrown 提交于
The ->enable|disable() callbacks are only used to get and put runtime PM references. Currently omap_hsmmc's ->set_ios() already does this itself. Other host drivers deals with runtime PM without using the ->enable|disable() callbacks and thus do the runtime PM reference counting themselves. Apply that approach for omap_hsmmc as well and then discard the ->enable|disable() callbacks. Signed-off-by: NNeilBrown <neil@brown.name> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 25 3月, 2015 2 次提交
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由 Georgi Djakov 提交于
Some versions of this controller do not advertise their 3.0v and 8bit bus-width support capabilities. It is required to explicitly set these capabilities for the specific controller versions. Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Sascha Hauer 提交于
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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