- 29 11月, 2010 3 次提交
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由 Michael Neuling 提交于
This adds the POWER7+ cputable entry for the PVR 0x004a0000. Rest is the same as vanilla POWER7. Signed-off-by: NMichael Neuling <mikey@neuling.org> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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由 Michael Neuling 提交于
These are not needed on POWER7 so remove them. Signed-off-by: NMichael Neuling <mikey@neuling.org> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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由 Michael Neuling 提交于
These are not needed so just remove them Signed-off-by: NMichael Neuling <mikey@neuling.org> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 14 10月, 2010 1 次提交
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由 Kumar Gala 提交于
The new e5500 core is similar to the e500mc core but adds 64-bit support. We support running it in 32-bit mode as it is identical to the e500mc. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 13 10月, 2010 1 次提交
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由 Tirumala Marri 提交于
This patch adds CPU, device tree, defconfig and bluestone board support for APM821xx SoC. Signed-off-by: NTirumala R Marri <tmarri@apm.com> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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- 23 8月, 2010 1 次提交
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由 Dave Kleikamp 提交于
There are two entries for .cpu_user_features in arch/powerpc/kernel/cputable.c. Remove the one that doesn't belong Signed-off-by: NDave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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- 26 7月, 2010 1 次提交
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由 Lee Nipper 提交于
The recent AMCC 405EX Rev D without Security uses a PVR value that matches the old 405EXr Rev A/B with Security. The 405EX Rev D without Security would be shown incorrectly as an 405EXr. The pvr_mask of 0xffff0004 is no longer sufficient to distinguish the 405EX from 405EXr. This patch replaces 2 entries in the cpu_specs table and adds 8 more, each using pvr_mask of 0xffff000f and appropriate pvr_value to distinguish the AMCC PowerPC 405EX and 405EXr instances. The cpu_name for these entries now includes the Rev, in similar fashion to the 440GX. Signed-off-by: NLee Nipper <lee.nipper@gmail.com> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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- 21 5月, 2010 1 次提交
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由 Scott Wood 提交于
Most of the MSCR bit assigments are different in e500mc versus e500, and they are now write-one-to-clear. Some e500mc machine check conditions are made recoverable (as long as they aren't stuck on), most notably L1 instruction cache parity errors. Signed-off-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 05 5月, 2010 3 次提交
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由 Torez Smith 提交于
This is a trivial 4xx plaform that uses the new simple bsp from Josh and is handy to use in simulators such as ISS or even Mambo who don't properly implement most of the actual devices in the SoC but really only the core. Signed-off-by: NTorez Smith <lnxtorez@linux.vnet.ibm.com> Signed-off-by: NDave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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由 Dave Kleikamp 提交于
The 47x core's MCSR varies from 44x, so it needs it's own machine check handler. Signed-off-by: NDave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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由 Dave Kleikamp 提交于
This patch adds the base support for the 476 processor. The code was primarily written by Ben Herrenschmidt and Torez Smith, but I've been maintaining it for a while. The goal is to have a single binary that will run on 44x and 47x, but we still have some details to work out. The biggest is that the L1 cache line size differs on the two platforms, but it's currently a compile-time option. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NTorez Smith <lnxtorez@linux.vnet.ibm.com> Signed-off-by: NDave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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- 05 3月, 2010 1 次提交
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由 Scott Wood 提交于
This implements perf_event support for the Freescale embedded performance monitor, based on the existing perf_event.c that supports server/classic chips. Some limitations: - Performance monitor interrupts are regular EE interrupts, and thus you can't profile places with interrupts disabled. We may want to implement soft IRQ-disabling, with perfmon interrupts exempted and treated as NMIs. - When trying to schedule multiple event groups at once, and using restricted events, situations could arise where scheduling fails even though it would be possible. Consider three groups, each with two events. One group has restricted events, the others don't. The two non-restricted groups are scheduled, then one is removed, which happens to occupy the two counters that can't do restricted events. The remaining non-restricted group will not be moved to the non-restricted-capable counters to make room if the restricted group tries to be scheduled. Signed-off-by: NScott Wood <scottwood@freescale.com> Acked-by: NPaul Mackerras <paulus@samba.org> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 13 12月, 2009 1 次提交
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由 Albert Herranz 提交于
This patch extends the cputable entry of the 750CL to also match the 750CL-based "Broadway" cpu found on the Nintendo Wii. As of this patch, the following "Broadway" design revision levels have been seen in the wild: - DD1.2 (87102) - DD2.0 (87200) Signed-off-by: NAlbert Herranz <albert_herranz@yahoo.es> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
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- 14 10月, 2009 1 次提交
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由 Dragos Tatulea 提交于
Here's a patch that adds the ppc750 CL cpu as supported by oprofile. Signed-off-by: NDragos Tatulea <dtatulea@ixiacom.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 28 8月, 2009 1 次提交
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由 Kumar Gala 提交于
Move the default cpu entry table for CONFIG_PPC_BOOK3E_64 to the very end since we will probably want to support both 32-bit and 64-bit kernels for some processors that are higher up in the list. Signed-off-by: NKumar Gala <galak@kernel.crashing.org> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 20 8月, 2009 2 次提交
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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由 Benjamin Herrenschmidt 提交于
This contains all the bits that didn't fit in previous patches :-) This includes the actual exception handlers assembly, the changes to the kernel entry, other misc bits and wiring it all up in Kconfig. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 21 5月, 2009 1 次提交
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由 Milton Miller 提交于
This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards compatibilty for CPUs before 2.06. Only useful for bare metal systems. Signed-off-by: NMilton Miller <miltonm@bga.com> Signed-off-by: NMichael Neuling <mikey@neuling.org> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 15 5月, 2009 1 次提交
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由 Benjamin Herrenschmidt 提交于
My previous pach for fixing the oprofile CPU type got somewhat mismerged (by my fault) when it collided with another related patch. This should finally (fingers crossed) fix the whole thing. We make sure we keep the -old- oprofile type and CPU type whenever one of them was specified in the first pass through the function. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 01 5月, 2009 2 次提交
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由 Benjamin Herrenschmidt 提交于
commit 2657dd4e introduced a bug where we would now always override the "real" oprofile CPU type with the "compatible" one provided by a pseudo-PVR in the device-tree which is incorrect and breaks oprofile on all current configs since the "compatible" ones aren't yet recognized. This fixes it. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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由 Michael Wolf 提交于
Oprofile is changing the naming it is using for the compatibility modes. Instead of having compat-power<x>, oprofile will go to family naming convention and use ibm-compat-v<x>. Currently only ibm-compat-v1 will be defined. The notion of compatibility events just started with POWER6. So there is no way that any other tool could exist that is using these oprofile_cpu_type strings we want to change. Signed-off-by: NMike Wolf <mjw@linux.vnet.ibm.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 23 4月, 2009 1 次提交
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由 Kumar Gala 提交于
This reverts commit e9965577. Our HW guys were able to fix this so it never sees the light of day. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 07 4月, 2009 1 次提交
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由 Kumar Gala 提交于
During the ISA 2.06 development the opcode for tlbilx changed and some early implementations used to old opcode. Add support for a MMU_FTR fixup to deal with this. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 24 3月, 2009 1 次提交
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由 Kumar Gala 提交于
Complete workaround for DTLB errata in e300c2/c3/c4 processors. Due to the bug, the hardware-implemented LRU algorythm always goes to way 1 of the TLB. This fix implements the proposed software workaround in form of a LRW table for chosing the TLB-way. Based on patch from David Jander <david@protonic.nl> Signed-off-by: NKumar Gala <galak@kernel.crashing.org> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 11 3月, 2009 3 次提交
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由 Octavian Purdila 提交于
This patch enables oprofile for all 3 FX variants and GX variant of the 750 processor. Signed-off-by: NOctavian Purdila <opurdila@ixiacom.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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由 Michael Ellerman 提交于
When identify_cpu() is called a second time with a logical PVR, it only copies a subset of the cpu_spec fields so as to avoid overwriting the performance monitor fields that were initialized based on the real PVR. However some of the other, non performance monitor related fields are also not copied: * pvr_mask * pvr_value * mmu_features * machine_check The fact that pvr_mask is not copied can result in show_cpuinfo() showing the cpu as "unknown", if we override an unknown PVR with a logical one - as reported by Shaggy. So change the logic to copy all fields, and then put back the PMC related ones in the case that we're overwriting a real PVR with a logical one. Signed-off-by: NMichael Ellerman <michael@ellerman.id.au> Acked-by: NDave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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由 Michael Ellerman 提交于
The for-loop body of identify_cpu() has gotten a little big, so move the loop body logic into a separate function. No other changes. Signed-off-by: NMichael Ellerman <michael@ellerman.id.au> Acked-by: NDave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 09 3月, 2009 1 次提交
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由 Kumar Gala 提交于
The e500mc core supports the new tlbilx instructions that do core local invalidates and also provide us the ability to take down all TLB entries matching a given PID. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 15 2月, 2009 1 次提交
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由 Madhulika Madishetty 提交于
This patch contains initial framework for the AMCC Redwood board. Signed-off-by: NMadhulika Madishetty <mmadishetty@amcc.com> Signed-off-by: NTirumala Marri <tmarri@amcc.com> Signed-off-by: NFeng Kan <fkan@amcc.com> Signed-off-by: NVidhyananth Venkatasamy <vvenkatasamy@amcc.com> Signed-off-by: NPreetesh Parekh <pparekh@amcc.com> Acked-by: NLoc Ho <lho@amcc.com> Acked-by: NFeng Kan <fkan@amcc.com> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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- 29 1月, 2009 1 次提交
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由 Kumar Gala 提交于
We currently have a few variants of fsl-booke processors (e500v1, e500v2, e500mc, and e200). They all have minor differences that we had previously been handling via ifdefs. To move towards having this support the following changes have been made: * PID1, PID2 only exist on e500v1 & e500v2 and should not be accessed on e500mc or e200. We use MMUCFG[NPIDS] to determine which case we are since we only touch PID1/2 in extremely early init code. * Not all IVORs exist on all the processors so introduce cpu_setup functions for each variant to setup the proper IVORs that are either unique or exist but have some variations between the processors Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 21 12月, 2008 2 次提交
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由 Benjamin Herrenschmidt 提交于
We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: NKumar Gala <galak@kernel.crashing.org> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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由 Benjamin Herrenschmidt 提交于
This adds supports to the "extended" DCR addressing via the indirect mfdcrx/mtdcrx instructions supported by some 4xx cores (440H6 and later). I enabled the feature for now only on AMCC 460 chips. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: NKumar Gala <galak@kernel.crashing.org> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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- 06 12月, 2008 1 次提交
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由 Grant Likely 提交于
The 440x5 core in the Virtex5 uses the 440A type machine check (ie, they have MCSRR0/MCSRR1). They thus need to call the appropriate fixup function to hook the right variant of the exception. Without this, all machine checks become fatal due to loss of context when entering the exception handler. Signed-off-by: NGrant Likely <grant.likely@secretlab.ca> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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- 17 10月, 2008 1 次提交
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由 Josh Boyer 提交于
This adds the AMCC PowerPC 405EZ chip to the cputable Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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- 20 8月, 2008 1 次提交
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由 Benjamin Herrenschmidt 提交于
The file arch/powerpc/kernel/sysfs.c is currently only compiled for 64-bit kernels. It contain code to register CPU sysdevs in sysfs and add various properties such as cache topology and raw access by root to performance monitor counters (PMCs). A lot of that can be re-used as is on 32-bits. This makes the file be built for both, with appropriate ifdef'ing for the few bits that are really 64-bit specific, and adds some support for the raw PMCs for 75x and 74xx processors. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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- 26 7月, 2008 1 次提交
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由 Nathan Lynch 提交于
Commit 9115d134 ("powerpc: Enable AT_BASE_PLATFORM aux vector") broke boot on 32-bit powerpc systems; we have to use PTRRELOC to initialize powerpc_base_platform this early in boot. Bug reported by Jon Smirl. Signed-off-by: NNathan Lynch <ntl@pobox.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 25 7月, 2008 1 次提交
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由 Nathan Lynch 提交于
Stash the first platform string matched by identify_cpu() in powerpc_base_platform, and supply that to the ELF loader for the value of AT_BASE_PLATFORM. Signed-off-by: NNathan Lynch <ntl@pobox.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 22 7月, 2008 1 次提交
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由 Torez Smith 提交于
While running on a system with new hardware and a kernel where the cpu_specs[] table does not recognize the new hardware, the identify_cpu() routine will select the default case as it searches through cpu_specs[] in an attempt to match the real PVR. Once the default case is selected, non of the oprofile counters and/or fields have been set up or defined. When identify_cpu() is called once more with the logical PVR, some of the cpu specific fields are replaced with the exception of the oprofile related ones. However, in the case where we have actually taken the default case while searching for the real PVR, we need to tell oprofile that we are now running in compatibility mode so it can pick up the correct counters. We do this by setting the oprofile_cpu_type field to be that taken from the cpu_specs[] for the cpu we are now emulating. This change will detect that we are now altering the real PVR and determine if we also need to update the oprofile_cpu_type field. Signed-off-by: NTorez Smith <lnxtorez@linux.vnet.ibm.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 15 7月, 2008 1 次提交
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由 Nathan Lynch 提交于
Background from Maynard Johnson: As of POWER6, a set of 32 common events is defined that must be supported on all future POWER processors. The main impetus for this compat set is the need to support partition migration, especially from processor P(n) to processor P(n+1), where performance software that's running in the new partition may not be knowledgeable about processor P(n+1). If a performance tool determines it does not support the physical processor, but is told (via the PPC_FEATURE_PSERIES_PERFMON_COMPAT bit) that the processor supports the notion of the PMU compat set, then the performance tool can surface just those events to the user of the tool. PPC_FEATURE_PSERIES_PERFMON_COMPAT indicates that the PMU supports at least this basic subset of events which is compatible across POWER processor lines. Signed-off-by: NNathan Lynch <ntl@pobox.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 04 7月, 2008 1 次提交
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由 John Linn 提交于
Updates the cputable to include the 440 processor found in the Xilinx Virtex5 FXT FPGA. Signed-off-by: NJohn Linn <john.linn@xilinx.com> Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
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