1. 29 11月, 2010 3 次提交
  2. 14 10月, 2010 1 次提交
  3. 13 10月, 2010 1 次提交
  4. 23 8月, 2010 1 次提交
  5. 26 7月, 2010 1 次提交
    • L
      powerpc/40x: Distinguish AMCC PowerPC 405EX and 405EXr correctly · ff349103
      Lee Nipper 提交于
      The recent AMCC 405EX Rev D without Security uses a PVR value
      that matches the old 405EXr Rev A/B with Security.
      The 405EX Rev D without Security would be shown
      incorrectly as an 405EXr. The pvr_mask of 0xffff0004
      is no longer sufficient to distinguish the 405EX from 405EXr.
      
      This patch replaces 2 entries in the cpu_specs table
      and adds 8 more, each using pvr_mask of 0xffff000f
      and appropriate pvr_value to distinguish the AMCC
      PowerPC 405EX and 405EXr instances.
      The cpu_name for these entries now includes the
      Rev, in similar fashion to the 440GX.
      Signed-off-by: NLee Nipper <lee.nipper@gmail.com>
      Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
      ff349103
  6. 21 5月, 2010 1 次提交
  7. 05 5月, 2010 3 次提交
  8. 05 3月, 2010 1 次提交
    • S
      powerpc/perf: e500 support · a1110654
      Scott Wood 提交于
      This implements perf_event support for the Freescale embedded performance
      monitor, based on the existing perf_event.c that supports server/classic
      chips.
      
      Some limitations:
      - Performance monitor interrupts are regular EE interrupts, and thus you
        can't profile places with interrupts disabled.  We may want to implement
        soft IRQ-disabling, with perfmon interrupts exempted and treated as NMIs.
      - When trying to schedule multiple event groups at once, and using
        restricted events, situations could arise where scheduling fails even
        though it would be possible.  Consider three groups, each with two events.
        One group has restricted events, the others don't.  The two non-restricted
        groups are scheduled, then one is removed, which happens to occupy the two
        counters that can't do restricted events.  The remaining non-restricted
        group will not be moved to the non-restricted-capable counters to make
        room if the restricted group tries to be scheduled.
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      Acked-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      a1110654
  9. 13 12月, 2009 1 次提交
  10. 14 10月, 2009 1 次提交
  11. 28 8月, 2009 1 次提交
  12. 20 8月, 2009 2 次提交
  13. 21 5月, 2009 1 次提交
  14. 15 5月, 2009 1 次提交
  15. 01 5月, 2009 2 次提交
  16. 23 4月, 2009 1 次提交
  17. 07 4月, 2009 1 次提交
  18. 24 3月, 2009 1 次提交
  19. 11 3月, 2009 3 次提交
  20. 09 3月, 2009 1 次提交
  21. 15 2月, 2009 1 次提交
  22. 29 1月, 2009 1 次提交
    • K
      powerpc/fsl-booke: Cleanup init/exception setup to be runtime · 105c31df
      Kumar Gala 提交于
      We currently have a few variants of fsl-booke processors (e500v1, e500v2,
      e500mc, and e200).  They all have minor differences that we had previously
      been handling via ifdefs.
      
      To move towards having this support the following changes have been made:
      
      * PID1, PID2 only exist on e500v1 & e500v2 and should not be accessed on
        e500mc or e200.  We use MMUCFG[NPIDS] to determine which case we are
        since we only touch PID1/2 in extremely early init code.
      
      * Not all IVORs exist on all the processors so introduce cpu_setup
        functions for each variant to setup the proper IVORs that are either
        unique or exist but have some variations between the processors
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      105c31df
  23. 21 12月, 2008 2 次提交
  24. 06 12月, 2008 1 次提交
  25. 17 10月, 2008 1 次提交
  26. 20 8月, 2008 1 次提交
  27. 26 7月, 2008 1 次提交
  28. 25 7月, 2008 1 次提交
  29. 22 7月, 2008 1 次提交
    • T
      powerpc: Indicate which oprofile counters to use while in compat mode · 79e25bac
      Torez Smith 提交于
      While running on a system with new hardware and a kernel where the
      cpu_specs[] table does not recognize the new hardware, the identify_cpu()
      routine will select the default case as it searches through cpu_specs[]
      in an attempt to match the real PVR. Once the default case is selected,
      non of the oprofile counters and/or fields have been set up or defined.
      
      When identify_cpu() is called once more with the logical PVR, some of
      the cpu specific fields are replaced with the exception of the oprofile
      related ones. However, in the case where we have actually taken the
      default case while searching for the real PVR, we need to tell
      oprofile that we are now running in compatibility mode so it can pick up
      the correct counters. We do this by setting the oprofile_cpu_type field
      to be that taken from the cpu_specs[] for the cpu we are now emulating.
      
      This change will detect that we are now altering the real PVR and determine
      if we also need to update the oprofile_cpu_type field.
      Signed-off-by: NTorez Smith <lnxtorez@linux.vnet.ibm.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      79e25bac
  30. 15 7月, 2008 1 次提交
    • N
      powerpc: Add PPC_FEATURE_PSERIES_PERFMON_COMPAT · 0f473314
      Nathan Lynch 提交于
      Background from Maynard Johnson:
      As of POWER6, a set of 32 common events is defined that must be
      supported on all future POWER processors.  The main impetus for this
      compat set is the need to support partition migration, especially from
      processor P(n) to processor P(n+1), where performance software that's
      running in the new partition may not be knowledgeable about processor
      P(n+1).  If a performance tool determines it does not support the
      physical processor, but is told (via the
      PPC_FEATURE_PSERIES_PERFMON_COMPAT bit) that the processor supports
      the notion of the PMU compat set, then the performance tool can
      surface just those events to the user of the tool.
      
      PPC_FEATURE_PSERIES_PERFMON_COMPAT indicates that the PMU supports at
      least this basic subset of events which is compatible across POWER
      processor lines.
      Signed-off-by: NNathan Lynch <ntl@pobox.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      0f473314
  31. 04 7月, 2008 1 次提交