提交 · 6e44f12ba64a58f25f8e6f35aa4c175f613001be · openeuler / raspberrypi-kernel

13 9月, 2005 14 次提交

[PATCH] i386: add memory clobbers to syscall macros · 6e44f12b

由 Andi Kleen 提交于 9月 12, 2005

As noted by matz@suse.de

The problem is, that on i386 the syscallN
macro is defined like so:

  long __res; \
  __asm__ volatile ("int $0x80" \
        : "=a" (__res) \
        : "0" (__NR_##name),"b" ((long)(arg1)),"c" ((long)(arg2)), \
          "d" ((long)(arg3)),"S" ((long)(arg4)),"D" ((long)(arg5))); \

If one of the arguments (in the _llseek syscall it's the arg4) is a pointer
which the syscall is expected to write to (to the memory pointed to by this
ptr), then this side-effect is not captured in the asm.

If anyone uses this macro to define it's own version of the syscall
(sometimes necessary when not using glibc) and it's inlined, then GCC
doesn't know that this asm write to "*dest", when called like so for instance:

  out = 1;
  llseek (fd, bla, blubb, &out, trara)
  use (out);

Here nobody tells GCC that "out" actually is written to (just a pointer to it
is passed to the asm).  Hence GCC might (and in the above bug did)
copy-propagate "1" into the second use of "out".

The easiest solution would be to add a "memory" clobber to the definition
of this syscall macro.  As this is a syscall, it shouldn't inhibit too many
optimizations.
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

6e44f12b

[PATCH] x86-64: Increase TLB flush array size · 2b4a0815

由 Andi Kleen 提交于 9月 12, 2005

The generic TLB flush functions kept upto 506 pages per
CPU to avoid too frequent IPIs.

This value was done for the L1 cache of older x86 CPUs,
but with modern CPUs it does not make much sense anymore.
TLB flushing is slow enough that using the L2 cache is fine.

This patch increases the flush array on x86-64 to cache
5350 pages. That is roughly 20MB with 4K pages. It speeds
up large munmaps in multithreaded processes on SMP considerably.

The cost is roughly 42k of memory per CPU, which is reasonable.

I only increased it on x86-64 for now, but it would probably
make sense to increase it everywhere. Embedded architectures
with SMP may keep it smaller to save some memory per CPU.
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

2b4a0815

[PATCH] x86-64: Don't include config.h in asm/timex.h · 165aeb82

由 Andi Kleen 提交于 9月 12, 2005

asm-x86-64/timex.h does not reference CONFIG constants.
Do not need to include config.h.
Signed-off-by: NGrant Grundler <iod00d@hp.com>
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

165aeb82

[PATCH] x86-64: Some cleanup and optimization to the processor data area. · 3f74478b

由 Andi Kleen 提交于 9月 12, 2005

- Remove unused irqrsp field
- Remove pda->me
- Optimize set_softirq_pending slightly
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

3f74478b

[PATCH] x86-64: Make remote TLB flush more scalable · e5bc8b6b

由 Andi Kleen 提交于 9月 12, 2005

Instead of using a global spinlock to protect the state
of the remote TLB flush use a lock and state for each sending CPU.

To tell the receiver where to look for the state use 8 different
call vectors.  Each CPU uses a specific vector to trigger flushes on other
CPUs. Depending on the received vector the target CPUs look into
the right per cpu variable for the flush data.

When the system has more than 8 CPUs they are hashed to the 8 available
vectors. The limited global vector space forces us to this right now.
In future when interrupts are split into per CPU domains this could be
fixed, at the cost of needing more IPIs in flat mode.

Also some minor cleanup in the smp flush code and remove some outdated
debug code.

Requires patch to move cpu_possible_map setup earlier.
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

e5bc8b6b

[PATCH] x86-64: Use ACPI PXM to parse PCI<->node assignments · 69e1a33f

由 Andi Kleen 提交于 9月 12, 2005

Since this is shared code I had to implement it for i386 too
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

69e1a33f

[PATCH] x86-64: Remove redundant max_mapnr and replace with end_pfn · b9aac10d

由 Andi Kleen 提交于 9月 12, 2005

The FLATMEM people added it, but there doesn't seem a good reason
because end_pfn is identical.
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

b9aac10d

[PATCH] x86-64: Avoid unnecessary double bouncing for swiotlb · 6142891a

由 Andi Kleen 提交于 9月 12, 2005

PCI_DMA_BUS_IS_PHYS has to be zero even when the GART IOMMU is disabled
and the swiotlb is used. Otherwise the block layer does unnecessary
double bouncing.
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

6142891a

[PATCH] x86-64: Support dualcore and 8 socket systems in k8 fallback node parsing · 3f098c26

由 Andi Kleen 提交于 9月 12, 2005

In particular on systems where the local APIC space and node space
is very different from the Linux CPU number space.

Previously the older NUMA setup code directly parsing the K8
northbridge registers had some issues on 8 socket or dual core
systems. This patch fixes them.

This is mainly done by fixing some confusion between Linux
CPU numbers and local APIC ids. We now pass the local APIC IDs
to later code, which avoids mismatches.

Also add some heuristics to detect cases where the Hypertransport
nodeids and the local APIC IDs don't match, but are shifted
by a constant offset.

This is still all quite hackish, hopefully BIOS writers fill
in correct SRATs instead.
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

3f098c26

[PATCH] x86-64: Don't cache align PDA on UP builds · b9169116

由 Andi Kleen 提交于 9月 12, 2005

Suggested by someone I forgot who sorry.
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

b9169116

[PATCH] x86-64: Don't assign CPU numbers in SRAT parsing · 0b07e984

由 Andi Kleen 提交于 9月 12, 2005

Do that later when the CPU boots. SRAT just stores the APIC<->Node
mapping node. This fixes problems on systems where the order
of SRAT entries does not match the MADT.
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

0b07e984

[PATCH] x86-64: Remove esr disable hack in APIC code · 61c11341

由 Andi Kleen 提交于 9月 12, 2005

This was just needed for the Numasaurus, which fortunately
doesn't support x86-64 CPUs.
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

61c11341

[PATCH] x86-64: Remove obsolete APIC "write around" bug workaround · eddfb4ed

由 Andi Kleen 提交于 9月 12, 2005

No x86-64 chipset has this bug

Generated code doesn't change because it was always disabled.
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

eddfb4ed

[PATCH] cpuset semaphore depth check optimize · b3426599

由 Paul Jackson 提交于 9月 12, 2005

Optimize the deadlock avoidance check on the global cpuset
semaphore cpuset_sem.  Instead of adding a depth counter to the
task struct of each task, rather just two words are enough, one
to store the depth and the other the current cpuset_sem holder.

Thanks to Nikita Danilov for the idea.
Signed-off-by: NPaul Jackson <pj@sgi.com>

[ We may want to change this further, but at least it's now
  a totally internal decision to the cpusets code ]
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

b3426599

12 9月, 2005 17 次提交

[PATCH] crc16: remove w1 specific comments. · f24ec7f6

由 Evgeniy Polyakov 提交于 9月 12, 2005

Remove w1 comments from crc16.h and move specific constants into
w1_ds2433.c where they are used.

Replace %d with %zd.
Signed-off-by: NEvgeniy Polyakov <johnpol@2ka.mipt.ru>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

f24ec7f6

[PATCH] ppc64: Remove unused code · 2d909d08

由 Anton Blanchard 提交于 9月 12, 2005

ppc64_attention_msg and ppc64_dump_msg are not used so remove them.
Signed-off-by: NAnton Blanchard <anton@samba.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

2d909d08

[PATCH] ppc64: Add ptrace data breakpoint support · fd9648df

由 Anton Blanchard 提交于 9月 10, 2005

Add hardware data breakpoint support.
Signed-off-by: NAnton Blanchard <anton@samba.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

fd9648df

[PATCH] ppc64: Add definitions for new PTRACE calls · a94d3085

由 Anton Blanchard 提交于 9月 10, 2005

- Add PTRACE_GET_DEBUGREG/PTRACE_SET_DEBUGREG. The definition is
  as follows:

/*
 * Get or set a debug register. The first 16 are DABR registers and the
 * second 16 are IABR registers.
 */
#define PTRACE_GET_DEBUGREG    25
#define PTRACE_SET_DEBUGREG    26

  DABR == data breakpoint and IABR = instruction breakpoint in IBM
  speak. We could split out the IABR into 2 more ptrace calls but I
  figured there was no need and 16 DABR registers should be more
  than enough (POWER4/POWER5 have one).

- Add 2 new SIGTRAP si_codes: TRAP_HWBKPT and TRAP_BRANCH. I couldnt
  find any standards on either of these so I copied what ia64 is
  doing. Again this might be better placed in
  include/asm-generic/siginfo.h
Signed-off-by: NAnton Blanchard <anton@samba.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

a94d3085

[PATCH] ppc64: ptrace cleanups · a0987224

由 Anton Blanchard 提交于 9月 10, 2005

- Remove the PPC_REG* defines
- Wrap some more stuff with ifdef __KERNEL__
- Add missing PT_TRAP, PT_DAR, PT_DSISR defines
- Add PTRACE_GETEVRREGS/PTRACE_SETEVRREGS, even though we dont use it on
  ppc64 we dont want to allocate them for something else.
Signed-off-by: NAnton Blanchard <anton@samba.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

a0987224

[PATCH] ppc64: Add PTRACE_{GET|SET}VRREGS · 962bca7f

由 Robert Jennings 提交于 9月 10, 2005

The ptrace get and set methods for VMX/Altivec registers present in the
ppc tree were missing for ppc64.  This patch adds the 32-bit and
64-bit methods.  Updated with the suggestions from Anton following the lines
of his code snippet.

Added:
 - flush_altivec_to_thread calls as suggested by Anton
 - piecewise copy of structure to preserve 32-bit vrsave data as per
   Anton

(I consolidated the 32 and 64bit versions with 2 helper macros - Anton)
Signed-off-by: NRobert C Jennings <rcjenn@austin.ibm.com>
Signed-off-by: NAnton Blanchard <anton@samba.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

962bca7f

ppc64: Set up PCI tree from Open Firmware device tree · 4267292b

由 Paul Mackerras 提交于 9月 12, 2005

This adds code which gives us the option on ppc64 of instantiating the
PCI tree (the tree of pci_bus and pci_dev structs) from the Open
Firmware device tree rather than by probing PCI configuration space.
The OF device tree has a node for each PCI device and bridge in the
system, with properties that tell us what addresses the firmware has
configured for them and other details.

There are a couple of reasons why this is needed.  First, on systems
with a hypervisor, there is a PCI-PCI bridge per slot under the PCI
host bridges.  These PCI-PCI bridges have special isolation features
for virtualization.  We can't write to their config space, and we are
not supposed to be reading their config space either.  The firmware
tells us about the address ranges that they pass in the OF device
tree.

Secondly, on powermacs, the interrupt controller is in a PCI device
that may be behind a PCI-PCI bridge.  If we happened to take an
interrupt just at the point when the device or a bridge on the path to
it was disabled for probing, we would crash when we try to access the
interrupt controller.

I have implemented a platform-specific function which is called for
each PCI bridge (host or PCI-PCI) to say whether the code should look
in the device tree or use normal PCI probing for the devices under
that bridge.  On pSeries machines we use the device tree if we're
running under a hypervisor, otherwise we use normal probing.  On
powermacs we use normal probing for the AGP bridge, since the device
for the AGP bridge itself isn't shown in the device tree (at least on
my G5), and the device tree for everything else.

This has been tested on a dual G5 powermac, a partition on a POWER5
machine (running under the hypervisor), and a legacy iSeries
partition.
Signed-off-by: NPaul Mackerras <paulus@samba.org>

4267292b

[PATCH] m68knommu: allow for SDRAM and GPIO differences on 5270/1 and 5274/5 processors · d871629b