1. 11 4月, 2017 11 次提交
  2. 07 4月, 2017 23 次提交
  3. 04 4月, 2017 1 次提交
  4. 02 4月, 2017 1 次提交
  5. 03 3月, 2017 1 次提交
  6. 04 10月, 2016 1 次提交
  7. 22 9月, 2016 2 次提交
    • J
      net/faraday: Mask out PHYSTS_CHG interrupt · edcd692f
      Joel Stanley 提交于
      The PHYSTS_CHG (the ftgmac100's PHY IRQ) is telling the system to go
      look at the PHY registers for a link status change.
      
      The interrupt was causing issues on Aspeed SoC where some board designs
      had an active high configuration, some active low, and in some cases
      repurposed for other functions. When misconfigured Linux would chew 100%
      of CPU cycles servicing interrupts:
      
       [   20.280000] ftgmac100 1e660000.ethernet eth0: [ISR] = 0x200: PHYSTS_CHG
       [   20.280000] ftgmac100 1e660000.ethernet eth0: [ISR] = 0x200: PHYSTS_CHG
       [   20.280000] ftgmac100 1e660000.ethernet eth0: [ISR] = 0x200: PHYSTS_CHG
       [   20.300000] ftgmac100 1e660000.ethernet eth0: [ISR] = 0x200: PHYSTS_CHG
      
      While in the ftgmac100 IP can be configured for high, low and edge
      sensitivity the current driver always polls the PHY, so we chose to mask
      out the interrupt.
      
      See https://patchwork.ozlabs.org/patch/672099/ for more discussion.
      Signed-off-by: NJoel Stanley <joel@jms.id.au>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      edcd692f
    • J
      net/faraday: Configure old MDIO interface on Aspeed SoCs · e07dc63b
      Joel Stanley 提交于
      The Aspeed SoCs have a new MDIO interface as an option in the G4 and G5
      SoCs. The old one is still available, so select it in order to remain
      compatible with the ftgmac100 driver.
      Signed-off-by: NJoel Stanley <joel@jms.id.au>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      e07dc63b