- 23 9月, 2014 2 次提交
-
-
由 Michel Dänzer 提交于
Use the same format for all ring indices, and fix the calculation of the post-overflow RPTR. Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Michel Dänzer 提交于
Otherwise the bit remains set in rdev->ih.rptr, so the wptr can never match that and we still have an infinite loop. This fix allows me to successfully recover from an IH ring buffer overflow. Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 28 8月, 2014 1 次提交
-
-
由 Alex Williamson 提交于
If we assign a Radeon device to a virtual machine, we can no longer assume a fixed hardware topology, like the GPU having a parent device. This patch simply adds a few pci_is_root_bus() tests to avoid passing a NULL pointer to PCI access functions, allowing the radeon driver to work in a QEMU 440FX machine with an assigned HD8570 on the emulated PCI root bus. Signed-off-by: NAlex Williamson <alex.williamson@redhat.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 27 8月, 2014 1 次提交
-
-
由 Christian König 提交于
This fixes a problem with GPU resets and TLB flushes on SI/CIK. Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 20 8月, 2014 2 次提交
-
-
由 Alex Deucher 提交于
Need to initialize the mask to 0 on init, otherwise it keeps increasing. bug: https://bugzilla.kernel.org/show_bug.cgi?id=82581 v2: also fix cu count v3: split count fix into separate patch Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NMichel Dänzer <michel.daenzer@amd.com> Cc: stable@vger.kernel.org
-
由 Alex Deucher 提交于
This fixes the CU count reported to userspace for OpenCL. bug: https://bugzilla.kernel.org/show_bug.cgi?id=82581Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NMichel Dänzer <michel.daenzer@amd.com> Cc: stable@vger.kernel.org
-
- 19 8月, 2014 1 次提交
-
-
由 Michel Dänzer 提交于
It isn't necessary for command streams generated by the kernel (at least not while we aren't storing ring or indirect buffers in VRAM). Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 15 8月, 2014 1 次提交
-
-
由 Alex Deucher 提交于
May fix hangs in some cases. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 05 8月, 2014 4 次提交
-
-
由 Mario Kleiner 提交于
Skip the "manual" pageflip completion checks via polling and guessing in the vblank handler radeon_crtc_handle_vblank() on asics which are known to reliably support hw pageflip completion irqs. Those pflip irqs are a more reliable and race-free method of handling pageflip completion detection, whereas the "classic" polling method has some small races in combination with dpm on, and with the reworked pageflip implementation since Linux 3.16. On old asics without pflip irqs, the classic method is used. On asics with known good pflip irqs, only pflip irqs are used by default, but a new module parameter "use_pflipirqs" allows to override this in case we encounter asics in the wild with unreliable or faulty pflip irqs. A module parameter of 0 allows to use the classic method only in such a case. A parameter of 1 allows to use both classic method and pflip irqs as additional band-aid to avoid some small races which could happen with the classic method alone. The setting 1 gives Linux 3.16 behaviour. Hw pflip irqs are available since R600. Tested on DCE-4, AMD Cedar - FirePro 2270. v2: agd5f: only enable pflip interrupts on DCE4+ as they are not reliable on older asics. Signed-off-by: NMario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Christian König 提交于
Seems to make VM flushes more stable on SI and CIK. v2: only use the PFP on the GFX ring on CIK Signed-off-by: NChristian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Michel Dänzer 提交于
Doesn't seem necessary, the GART table memory should be persistent. Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
This adds SI support for the new ucode format. v2: add size validation, integrate debug info v3: update to latest version Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 23 7月, 2014 1 次提交
-
-
由 Christian König 提交于
We must mask out the overflow bit as well, otherwise the wptr will never match the rptr again and the interrupt handler will loop forever. Signed-off-by: NChristian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NMichel Dänzer <michel.daenzer@amd.com>
-
- 11 7月, 2014 1 次提交
-
-
由 Christian König 提交于
Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 10 6月, 2014 3 次提交
-
-
由 Alex Deucher 提交于
Query to find out how many compute units on a GPU. Useful for OpenCL usermode drivers. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Christian König 提交于
Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Christian König 提交于
Replace occurrences of "v & 0xffffffff" with lower_32_bits(v) when it's next to an upper_32_bits(v). Also remove unnecessary "upper_32_bits(v) & 0xffffffff" code snippets. Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 02 6月, 2014 3 次提交
-
-
由 Christian König 提交于
Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Christian König 提交于
This patch makes it possible to decide how many address bits are spend on the page directory vs the page tables. v2: remove unintended change Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Christian König 提交于
This patch implements support for VRAM page table entry compression. PTE construction is enhanced to identify physically contiguous page ranges and mark them in the PTE fragment field. L1/L2 TLB support is enabled for 64KB (SI/CIK) and 256KB (NI) PTE fragments, significantly improving TLB utilization for VRAM allocations. Linear store bandwidth is improved from 60GB/s to 125GB/s on Pitcairn. Unigine Heaven 3.0 sees an average improvement from 24.7 to 27.7 FPS on default settings at 1920x1200 resolution with vsync disabled. See main comment in radeon_vm.c for a technical description. v2 (chk): rebased and simplified. v3 (chk): add missing hw setup v4 (chk): rebased on current drm-fixes-3.15 v5 (chk): fix comments and commit text Signed-off-by: NJay Cornwall <jay@jcornwall.me> Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 01 5月, 2014 1 次提交
-
-
由 Christian König 提交于
Testing the update pending bit directly after issuing an update is nonsense cause depending on the pixel clock the CRTC needs a bit of time to execute the flip even when we are in the VBLANK period. This is just a non invasive patch to solve the problem at hand, a more complete and cleaner solution should follow in the next merge window. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=76564 v2: fix source IDs for CRTC2-6 Signed-off-by: NChristian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
-
- 17 4月, 2014 2 次提交
-
-
由 Alex Deucher 提交于
Avoid a possible segfault. Noticed-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
-
由 Alex Deucher 提交于
May fix stability issues with some newer cards. v2: print out mc firmware version used and size Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
-
- 07 3月, 2014 1 次提交
-
-
由 Alex Deucher 提交于
Moving the pm resume up in the init order to fix dpm seems to have regressed somes cases with the old pm code. Move it back to late resume. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 19 2月, 2014 2 次提交
-
-
由 Christian König 提交于
The reason for the false positives was fixed quite some time ago and since most engines can still execute NOPs while being locked up it leads to false negatives. Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Christian König 提交于
In all cases where it really matters we are using the read functions anyway. Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 07 2月, 2014 1 次提交
-
-
由 Christian König 提交于
Otherwise decoding isn't really useable. bug: https://bugs.freedesktop.org/show_bug.cgi?id=71448Signed-off-by: NChristian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 30 1月, 2014 2 次提交
-
-
由 Alex Deucher 提交于
DCE5 and newer hardware only has 1 DAC. Use the correct offset. This may fix display problems on certain board configurations. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
-
由 Alex Deucher 提交于
If we are not able to properly initialize one of the gpu engines for buffer paging, we limit vram to the size of the cpu visible aperture. We generally either use the gfx or dma engine to do this. Clean up the size limiting code to only adjust the size based on what ring is selected for buffer paging rather than making assumptions about which engine is selected for paging. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com>
-
- 21 1月, 2014 1 次提交
-
-
由 Alex Deucher 提交于
For consistency. These buffers aren't used when pg is disabled. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 09 1月, 2014 1 次提交
-
-
由 Alex Deucher 提交于
pci config reset is a low level reset that resets the entire chip from the bus interface. It can be more reliable if soft reset fails. v2: hide behind module parameter Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 25 12月, 2013 4 次提交
-
-
由 Alex Deucher 提交于
Fill in asic family specific versions rather than using the generic version. This lets us handle asic specific differences more easily. In this case, we disable sw swapping of the rtpr writeback value on r6xx+ since the hw does it for us. Fixes bogus rptr readback on BE systems. v2: remove missed cpu_to_le32(), add comments Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
We need more control over the ordering of dpm init with respect to the rest of the asic. Specifically, the SMC has to be initialized before the rlc and cg/pg. The pm code currently initializes late in the driver, but we need it to happen much earlier so move pm handling into the asic specific callbacks. This makes dpm more reliable and makes clockgating work properly on CIK parts and should help on SI parts as well. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
We need to reorder the driver init sequence to better accomodate dpm which needs to be loaded earlier in the init sequence. Move fw init up so that it's available for dpm init. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
I'm not entirely sure this is required and it won't work with the dpm restructing anyway. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 23 12月, 2013 2 次提交
-
-
由 Marek Olšák 提交于
This will allow userspace to correctly program the PA_SC_RASTER_CONFIG register, so it can be considered a fix. Signed-off-by: NMarek Olšák <marek.olsak@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
-
由 Marek Olšák 提交于
Only the render backends of the first shader engine were enabled. The others were erroneously disabled. Enabling the other render backends improves performance a lot. Unigine Sanctuary on Bonaire: Before: 15 fps After: 90 fps Judging from the fan noise, the GPU was also underclocked when the other render backends were disabled, resulting in horrible performance. The fan is a lot noisy under load now. Signed-off-by: NMarek Olšák <marek.olsak@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
-
- 05 12月, 2013 1 次提交
-
-
由 Alex Deucher 提交于
Some boards seem to have garbage in the upper 16 bits of the vram size register. Check for this and clamp the size properly. Fixes boards reporting bogus amounts of vram. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
-
- 02 11月, 2013 2 次提交
-
-
由 Christian König 提交于
The DMA ring seems to be stable now. v2: remove pt_ring_index as well Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
The buffers needs to be in little endian format. Noticed-by: NSylvain BERTRAND <sylware@legeek.net> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-