1. 11 7月, 2008 4 次提交
  2. 09 7月, 2008 2 次提交
  3. 08 7月, 2008 7 次提交
  4. 27 6月, 2008 2 次提交
  5. 25 6月, 2008 1 次提交
  6. 05 6月, 2008 1 次提交
  7. 04 6月, 2008 1 次提交
  8. 26 5月, 2008 1 次提交
  9. 25 5月, 2008 1 次提交
  10. 24 5月, 2008 4 次提交
  11. 07 5月, 2008 1 次提交
  12. 01 5月, 2008 1 次提交
  13. 29 4月, 2008 1 次提交
  14. 27 4月, 2008 3 次提交
  15. 20 4月, 2008 5 次提交
  16. 18 4月, 2008 1 次提交
  17. 17 4月, 2008 4 次提交
    • I
      x86: standalone trampoline code · 77ad386e
      Ingo Molnar 提交于
      move the trampoline setup code out of smpboot.c - UP kernels can have
      suspend support too.
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      77ad386e
    • A
      x86: merge mpparse_{32,64}.c · 85bdddec
      Alexey Starikovskiy 提交于
      Signed-off-by: NAlexey Starikovskiy <astarikovskiy@suse.de>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      85bdddec
    • J
      x86: support for new UV apic · ac23d4ee
      Jack Steiner 提交于
      UV supports really big systems. So big, in fact, that the APICID register
      does not contain enough bits to contain an APICID that is unique across all
      cpus.
      
      The UV BIOS supports 3 APICID modes:
      
      	- legacy mode. This mode uses the old APIC mode where
      	  APICID is in bits [31:24] of the APICID register.
      
      	- x2apic mode. This mode is whitebox-compatible. APICIDs
      	  are unique across all cpus. Standard x2apic APIC operations
      	  (Intel-defined) can be used for IPIs. The node identifier
      	  fits within the Intel-defined portion of the APICID register.
      
      	- x2apic-uv mode. In this mode, the APICIDs on each node have
      	  unique IDs, but IDs on different node are not unique. For example,
      	  if each mode has 32 cpus, the APICIDs on each node might be
      	  0 - 31. Every node has the same set of IDs.
      	  The UV hub is used to route IPIs/interrupts to the correct node.
      	  Traditional APIC operations WILL NOT WORK.
      
      In x2apic-uv mode, the ACPI tables all contain a full unique ID (note:
      exact bit layout still changing but the following is close):
      
      	nnnnnnnnnnlc0cch
      		n = unique node number
      		l = socket number on board
      		c = core
      		h = hyperthread
      
      Only the "lc0cch" bits are written to the APICID register. The remaining bits are
      supplied by having the get_apic_id() function "OR" the extra bits into the value
      read from the APICID register. (Hmmm.. why not keep the ENTIRE APICID register
      in per-cpu data....)
      
      The x2apic-uv mode is recognized by the MADT table containing:
      	  oem_id = "SGI"
      	  oem_table_id = "UV-X"
      Signed-off-by: NJack Steiner <steiner@sgi.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      ac23d4ee
    • R
      x86: fix build breakage when PCI is define and PARAVIRT is not · aa7d8e25
      Ravikiran G Thirumalai 提交于
      - Fix the the build breakage when PARAVIRT is defined
        but PCI is not
        This fixes problem reported at:
      	http://marc.info/?l=linux-kernel&m=120525966600698&w=2
      - Make is_vsmp_box() available even when PARAVIRT is not defined.
        This is needed to determine if tsc's are reliable as a time source
        even when PARAVIRT is not defined.
      - split vsmp_init to use is_vsmp_box() and set_vsmp_pv_ops()
        set_vsmp_pv_ops will do nothing if PCI is not enabled in the config.
      Signed-off-by: NRavikiran Thirumalai <kiran@scalex86.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      aa7d8e25