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  1. 11 3月, 2014 1 次提交
  3. 28 1月, 2014 1 次提交
  5. 17 1月, 2014 5 次提交
  7. 13 1月, 2014 2 次提交
    • G
      powerpc/512x: clk: support MPC5121/5123/5125 SoC variants · 319bbe0e
      由 Gerhard Sittig 提交于 
      improve the common clock support code for MPC512x

- expand the CCM register set declaration with MPC5125 related registers
  (which reside in the previously "reserved" area)
- tell the MPC5121, MPC5123, and MPC5125 SoC variants apart, and derive
  the availability of components and their clocks from the detected SoC
  (MBX, AXE, VIU, SPDIF, PATA, SATA, PCI, second FEC, second SDHC,
  number of PSC components, type of NAND flash controller,
  interpretation of the CPMF bitfield, PSC/CAN mux0 stage input clocks,
  output clocks on SoC pins)
- add backwards compatibility (allow operation against a device tree
  which lacks clock related specs) for MPC5125 FECs, too

telling SoC variants apart and adjusting the clock tree's generation
occurs at runtime, a common generic binary supports all of the chips

the MPC5125 approach to the NFC clock (one register with two counters
for the high and low periods of the clock) is not implemented, as there
are no users and there is no common implementation which supports this
kind of clock -- the new implementation would be unused and could not
get verified, so it shall wait until there is demand
Signed-off-by: NGerhard Sittig <gsi@denx.de>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
      319bbe0e
    • G
      dts: mpc512x: introduce dt-bindings/clock/ header · 4cc5e1ca
      由 Gerhard Sittig 提交于 
      introduce a dt-bindings/ header file for MPC512x clocks,
providing symbolic identifiers for those SoC clocks which
clients will reference from their device tree nodes

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: devicetree@vger.kernel.org
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NGerhard Sittig <gsi@denx.de>
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
      4cc5e1ca
  9. 09 1月, 2014 6 次提交
  11. 08 1月, 2014 1 次提交
    • T
      ARM: dts: Add omap specific pinctrl defines to use padconf addresses · 43a348ea
      由 Tony Lindgren 提交于 
      As we have one to three pinctrl-single instances for each SoC it is
a bit confusing to configure the padconf register offset from the
base of the padconf register base.

Let's add macros that allow using the physical address of the
padconf register directly, or in most cases, just the last 16-bits
of the address as they are shown in the documentation.

Note that most documentation shows two padconf registers for each
32-bit address, so adding 2 to the documentation address is needed for
the second padconf register as we treat them as 16-bit registers
for omap3+.

For example, omap36xx documentation shows sdmmc2_clk at 0x48002158,
so we can just use the last 16-bits of that value:

	pinctrl-single,pins = <
		OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)
		...
	>;

And we don't need to separately calculate the offset from the 0x2030
base:

	pinctrl-single,pins = <
		0x128 (PIN_INPUT_PULLUP | MUX_MODE0)
		...
	>;

Naturally both ways of defining the registers can be used, and I'm
not saying we should replace all the existing defines. But it may
be handy to use these macros for new entries and when doing other
related .dts file clean-up.
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
[tony@atomide.com: updated for 3430 vs 3630 core2 range]
Signed-off-by: NTony Lindgren <tony@atomide.com>
      43a348ea
  13. 31 12月, 2013 5 次提交
  15. 26 12月, 2013 2 次提交
  17. 24 12月, 2013 6 次提交
  19. 19 12月, 2013 2 次提交
  21. 17 12月, 2013 2 次提交
  23. 12 12月, 2013 1 次提交
  25. 09 12月, 2013 1 次提交
  27. 04 12月, 2013 2 次提交
    • E
      thermal: introduce device tree parser · 4e5e4705
      由 Eduardo Valentin 提交于 
      This patch introduces a device tree bindings for
describing the hardware thermal behavior and limits.
Also a parser to read and interpret the data and feed
it in the thermal framework is presented.

This patch introduces a thermal data parser for device
tree. The parsed data is used to build thermal zones
and thermal binding parameters. The output data
can then be used to deploy thermal policies.

This patch adds also documentation regarding this
API and how to define tree nodes to use
this infrastructure.

Note that, in order to be able to have control
on the sensor registration on the DT thermal zone,
it was required to allow changing the thermal zone
.get_temp callback. For this reason, this patch
also removes the 'const' modifier from the .ops
field of thermal zone devices.

Cc: Zhang Rui <rui.zhang@intel.com>
Cc: linux-pm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NEduardo Valentin <eduardo.valentin@ti.com>
      4e5e4705
    • H
      clk: hisilicon: add common clock support · 0aa0c95f
      由 Haojian Zhuang 提交于 
      Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is
used to support the clock gate that enable/disable/status registers
are seperated.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
      0aa0c95f
  29. 02 12月, 2013 1 次提交
  31. 27 11月, 2013 2 次提交