提交 · 6ab3d5624e172c553004ecc862bfeac16d9d68b7 · openeuler / raspberrypi-kernel

01 7月, 2006 1 次提交

Remove obsolete #include <linux/config.h> · 6ab3d562

由 Jörn Engel 提交于 6月 30, 2006

Signed-off-by: NJörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: NAdrian Bunk <bunk@stusta.de>

6ab3d562

30 6月, 2006 4 次提交
- R
  [MIPS] 74K: Assume it will also have an AR bit in config7 · 2e78ae3f
  由 Ralf Baechle 提交于 6月 23, 2006
```
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  2e78ae3f
- R
  [MIPS] Treat CPUs with AR bit as physically indexed. · beab375a
  由 Ralf Baechle 提交于 6月 19, 2006
```
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  beab375a
- C
  [MIPS] Fix handling of 0 length I & D caches. · 73f40352
  由 Chris Dearman 提交于 6月 20, 2006
```
Don't ask.
Signed-off-by: NChris Dearman <chris@mips.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  73f40352
- C
  [MIPS] MIPS32/MIPS64 secondary cache management · 9318c51a
  由 Chris Dearman 提交于 6月 20, 2006
```
Signed-off-by: NChris Dearman <chris@mips.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  9318c51a
06 6月, 2006 1 次提交

[MIPS] Save write-only Config.OD from being clobbered · 9370b351

由 Sergei Shtylyov 提交于 5月 26, 2006

Save the Config.OD bit from being clobbered by coherency_setup(). This
bit, when set, fixes various errata in the early steppings of Au1x00
SOCs. Unfortunately, the bit was write-only on the most early of them.
In addition, also restore the bit after a wakeup from sleep.
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

9370b351

01 6月, 2006 3 次提交

[MIPS] Treat R14000 like R10000. · 44d921b2

由 Kumba 提交于 5月 16, 2006

Signed-off-by: NJoshua Kinard <kumba@gentoo.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

44d921b2

[MIPS] Fix deadlock on MP with cache aliases. · 7f3f1d01

由 Ralf Baechle 提交于 5月 12, 2006

A proper fix would involve introducing the notion of shared caches but
at this stage of 2.6.17 that's going to be too intrusive and not needed
for current hardware; aside I think some discussion will be needed.

So for now on the affected SMP configurations which happen to suffer from
cache aliases we make use of the fact that a single cache will be shared
by all processors. This solves the deadlock issue and will improve
performance by getting rid of the smp_call_function overhead.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

7f3f1d01

[MIPS] Add missing 34K processor IDs · 98a41de9

由 Nigel Stephens 提交于 4月 27, 2006

    
The 34K is very much like a 24K on steroids.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

98a41de9

19 4月, 2006 3 次提交

A
[MIPS] Use __ffs() instead of ffs() for waybit calculation. · 3c68da79
由 Atsushi Nemoto 提交于 4月 08, 2006
```
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
3c68da79
R
[MIPS] Handle IDE PIO cache aliases on SMP. · 7e3bfc7c
由 Ralf Baechle 提交于 4月 05, 2006
```
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
7e3bfc7c

[MIPS] Fix tx49_blast_icache32_page_indexed. · 67a3f6de

由 Atsushi Nemoto 提交于 4月 04, 2006

Fix the cache index value in tx49_blast_icache32_page_indexed().
This is a damage by de62893b commit.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

67a3f6de

21 3月, 2006 1 次提交

[MIPS] TX49XX has prefetch. · de862b48

由 Atsushi Nemoto 提交于 3月 17, 2006

    
The TX49XX has the prefetch instruction.  It supports only Pref_Load
(hint 0).  Actually changes in this patch except for Kconfig are not
have any effects, I added these changes to prevent misuse of unsupported
hints.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

de862b48

19 3月, 2006 1 次提交

[MIPS] local_r4k_flush_cache_page fix · de62893b

由 Atsushi Nemoto 提交于 3月 13, 2006

    
If dcache_size != icache_size or dcache_size != scache_size, or
set-associative cache, icache/scache does not flushed properly.  Make
blast_?cache_page_indexed() masks its index value correctly.  Also,
use physical address for physically indexed pcache/scache.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

de62893b

01 3月, 2006 1 次提交

[MIPS] Initialize S-cache function pointers even on S-cache-less CPUs. · 4debe4f9

由 Ralf Baechle 提交于 2月 27, 2006

    
When a CPU has no scache, the scache flushing functions currently
aren't getting initialized and the NULL pointer is eventually called
as a function.  Initialize the scache flushing functions as a noop
when there's no scache.
    
Initial patch by me and most of the debugging done by Martin Michlmayr.
Signed-off-by: NMartin Michlmayr <tbm@cyrius.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

4debe4f9

15 2月, 2006 1 次提交

[MIPS] Add protected_blast_icache_range, blast_icache_range, etc. · 41700e73

由 Atsushi Nemoto 提交于 2月 10, 2006

    
Add blast_xxx_range(), protected_blast_xxx_range() etc. for common
use.  They are built by __BUILD_BLAST_CACHE_RANGE().
Use protected_cache_op() macro for various protected_ routines.
Output code should be logically same.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

41700e73

07 2月, 2006 1 次提交

[MIPS] Remove wrong __user tags. · d4264f18

由 Atsushi Nemoto 提交于 1月 29, 2006

    
This fixes sparse warnings 'dereference of noderef expression'.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

d4264f18

10 1月, 2006 1 次提交
- R
  MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1. · e7958bb9
  由 Ralf Baechle 提交于 12月 08, 2005
```
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  e7958bb9
30 10月, 2005 21 次提交
- R
  Rename page argument of flush_cache_page to something more descriptive. · 6ec25809
  由 Ralf Baechle 提交于 10月 12, 2005
```
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  6ec25809
- R
  Cleanup the mess in cpu_cache_init. · 02cf2119
  由 Ralf Baechle 提交于 10月 01, 2005
```
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  02cf2119
- T
  Add/Fix missing bit of R4600 hit cacheop workaround. · 10a3dabd
  由 Thiemo Seufer 提交于 9月 09, 2005
```
Signed-off-by: NThiemo Seufer <ths@networkno.de>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  10a3dabd
- T
  Minor code cleanup. · 02fe2c9c
  由 Thiemo Seufer 提交于 9月 09, 2005
```
Signed-off-by: NThiemo Seufer <ths@networkno.de>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  02fe2c9c
- T
  More .set push/pop. · d8748a3a
  由 Thiemo Seufer 提交于 9月 02, 2005
```
Signed-off-by: NThiemo Seufer <ths@networkno.de>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  d8748a3a
- T
  Let r4600 PRID detection match only legacy CPUs, cleanups. · 330cfe01
  由 Thiemo Seufer 提交于 9月 01, 2005
```
Signed-off-by: NThiemo Seufer <ths@networkno.de>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  330cfe01
- R
  Avoid SMP cacheflushes. This is a minor optimization of startup but · 1d40cfcd
  由 Ralf Baechle 提交于 7月 15, 2005
```
will also avoid smp_call_function from doing stupid things when called
from a CPU that is not yet marked online.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  1d40cfcd
- R
  More AP / SP bits for the 34K, the Malta bits and things. Still wants · e01402b1
  由 Ralf Baechle 提交于 7月 14, 2005
```
a little polishing.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  e01402b1
- R
  Mark a few variables __read_mostly. · ec74e361
  由 Ralf Baechle 提交于 7月 13, 2005
```
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  ec74e361
- R
  MIPS R2 instruction hazard handling. · cc61c1fe
  由 Ralf Baechle 提交于 7月 12, 2005
```
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  cc61c1fe
- T
  Better interface to run uncached cache setup code. · ba5187db
  由 Thiemo Seufer 提交于 4月 25, 2005
```
Signed-off-by: NThiemo Seufer <ths@networkno.de>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  ba5187db
- R
  Sparseify MIPS. · fe00f943
  由 Ralf Baechle 提交于 3月 01, 2005
```
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  fe00f943
- P
  Base Au1200 2.6 support. · e3ad1c23
  由 Pete Popov 提交于 3月 01, 2005
```
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  e3ad1c23
- T
  Use intermediate variable. · 26a51b27
  由 Thiemo Seufer 提交于 2月 19, 2005
```
Signed-off-by: NThiemo Seufer <ths@networkno.de>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  26a51b27
- R
  Moves a test which determines if we actually need to perform a · 79acf83e
  由 Ralf Baechle 提交于 2月 10, 2005
```
cacheflush to the right place.  That's a bug which is harmless on UP
but a severe bug on SMP.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  79acf83e
- R
  Update MIPS to use the 4-level pagetable code thereby getting rid of · c6e8b587
  由 Ralf Baechle 提交于 2月 10, 2005
```
the compacrapability headers.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  c6e8b587
- R
  25Kf is also physically indexed. · 505403b6
  由 Ralf Baechle 提交于 2月 07, 2005
```
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  505403b6
- R
  20Kc and SB1 don't suffer from aliases. · a95970f3
  由 Ralf Baechle 提交于 2月 07, 2005
```
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  a95970f3
- R
  Move missplaced code line to the right place. · ae6aafe3
  由 Ralf Baechle 提交于 2月 06, 2005
```
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  ae6aafe3
- R
  Use hardware mechanism to deal with cache aliases in the 24K. · d1e344e5
  由 Ralf Baechle 提交于 2月 04, 2005
```
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  d1e344e5
- R
  Remove old wrong bits of cache code. · 28ecca47
  由 Ralf Baechle 提交于 2月 04, 2005
```
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
```
  28ecca47
05 9月, 2005 1 次提交

[PATCH] mips: nuke trailing whitespace · 42a3b4f2

由 Ralf Baechle 提交于 9月 03, 2005

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

42a3b4f2