Add initial support for boards based on the Imagination Pistachio SoC.
Pistachio is based on a dual-core MIPS interAptiv CPU and will boot
using device-tree.
Signed-off-by: NJames Hartley <james.hartley@imgtec.com>
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9569/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Platforms which use raw zboot images may need to link the image at
a fixed address if there is no other way to communicate the load
address to the bootloader.  Allow the per-platform Kbuild files
to specify an optional zboot image load address (zload-y) and fall
back to calc_vmlinuz_load_addr if unset.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9566/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

11 platforms require at least one of these workarounds to be enabled; 22
platforms do not.  In the latter case we can fall back to a generic version.

Note that this also deletes an orphaned reference to RM9000_CDEX_SMP_WAR.
Suggested-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Reviewed-by: NJames Hogan <james.hogan@imgtec.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9567/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add OCTEON SHA512 module.
Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: linux-crypto@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9496/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add OCTEON SHA256 module.
Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: linux-crypto@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9493/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add OCTEON SHA1 module.
Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: linux-crypto@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9495/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add instruction definitions for SHA1/256/512.
Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: linux-crypto@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9491/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Always disable preemption on behalf of the drivers when crypto engine
is taken into use. This will simplify the usage.
Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: linux-crypto@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9494/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Don't disable bottom half while the crypto engine is in use, as it
should be unnecessary: All kernel crypto engine usage is wrapped with
crypto engine state save/restore, so if we get interrupted by softirq
that uses crypto they should save and restore our context.

This actually fixes an issue when running OCTEON MD5 with interrupts
disabled (tcrypt mode=302). There's a WARNING because the module is
trying to enable the bottom half with irqs disabled:

[   52.656610] ------------[ cut here ]------------
[   52.661439] WARNING: CPU: 1 PID: 428 at /home/aaro/git/linux/kernel/softirq.c:150 __local_bh_enable_ip+0x9c/0xd8()
[   52.671780] Modules linked in: tcrypt(+)
[...]
[   52.763539] [<ffffffff8114082c>] warn_slowpath_common+0x94/0xd8
[   52.769465] [<ffffffff81144614>] __local_bh_enable_ip+0x9c/0xd8
[   52.775390] [<ffffffff81119574>] octeon_md5_final+0x12c/0x1e8
[   52.781144] [<ffffffff81337050>] shash_compat_digest+0xd0/0x1b0
Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: linux-crypto@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9490/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The 'arg' argument to copy_thread() is only ever used when forking a new
kernel thread. Hence, rename it to 'kthread_arg' for clarity (and consistency
with do_fork() and other arch-specific implementations of copy_thread()).
Signed-off-by: NAlex Dowad <alexinbeijing@gmail.com>
Cc: linux-kernel@vger.kernel.org
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Alex Smith <alex@alex-smith.me.uk>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Eunbong Song <eunb.song@samsung.com>
Cc: linux-mips@linux-mips.org (open list:MIPS)
Patchwork: https://patchwork.linux-mips.org/patch/9546/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Support parsing SPROMs with prefixes defined like devpath1=pci/1/1
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: https://patchwork.linux-mips.org/patch/9552/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Enable disabled interrupt, on unsuccessful operation.

Found by Coccinelle.
Signed-off-by: NTapasweni Pathak <tapaswenipathak@gmail.com>
Acked-by: NJulia Lawall <julia.lawall@lip6.fr>
Reviewed-by: NJames Hogan <james.hogan@imgtec.com>
Signed-off-by: NMarcelo Tosatti <mtosatti@redhat.com>

Currently the guest exit trace event saves the VCPU pointer to the
structure, and the guest PC is retrieved by dereferencing it when the
event is printed rather than directly from the trace record. This isn't
safe as the printing may occur long afterwards, after the PC has changed
and potentially after the VCPU has been freed. Usually this results in
the same (wrong) PC being printed for multiple trace events. It also
isn't portable as userland has no way to access the VCPU data structure
when interpreting the trace record itself.

Lets save the actual PC in the structure so that the correct value is
accessible later.

Fixes: 669e846e ("KVM/MIPS32: MIPS arch specific APIs for KVM")
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Cc: <stable@vger.kernel.org> # v3.10+
Acked-by: NSteven Rostedt <rostedt@goodmis.org>
Signed-off-by: NMarcelo Tosatti <mtosatti@redhat.com>

Commit e9de688d ("irqchip: mips-gic: Support local interrupts")
updated several platforms. This is a copy paste error.
Signed-off-by: NNiklas Cassel <niklass@axis.com>
Reviewed-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9245/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

In commit c441d4a5 ("MIPS: mm: Only build one microassembler that
is suitable"), the Makefile at arch/mips/mm was rewritten to only
build the "right" microassembler file, depending on whether
CONFIG_CPU_MICROMIPS is set or not.

In the files, however, there are still preprocessor definitions
depending on CONFIG_CPU_MICROMIPS. The #ifdef around them can now
never evaluate to true, so let's remove them altogether.

This inconsistency was found using the undertaker-checkpatch tool.
Signed-off-by: NAndreas Ruprecht <rupran@einserver.de>
Reviewed-by: NMaciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Valentin Rothberg <valentinrothberg@gmail.com>
Cc: Paul Bolle <pebolle@tiscali.nl>
Patchwork: https://patchwork.linux-mips.org/patch/9267/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

- Use of_irq_init() to initialize interrupt controllers
- Get rid of some unlikely()
- Add CIB to support SATA and other interrupts
- Add support for CIU SUM2 interrupt sources
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NLeonid Rosenboim <lrosenboim@caviumnetworks.com>
Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com>
Signed-off-by: NPeter Swain <peter.swain@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8947/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The acknowledge bits don't exist for level triggered irqs, so setting
them causes the simulator to terminate.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NLeonid Rosenboim <lrosenboim@caviumnetworks.com>
Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8946/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Read clock rate from the correct CSR. Don't clear COP0_DCACHE for OCTEONIII.
Signed-off-by: NChandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com>
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8945/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

CN38XX pass 1 required icache prefetching to be turned off. This chip never
reached production and is long dead. Other processor specific icache settings
are done by the bootloader. Remove these bits from the kernel.
Signed-off-by: NChad Reese <kreese@caviumnetworks.com>
Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/8944/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8943/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add coverage for OCTEON III models.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8942/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Make messages refer to all CN6XXX.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8941/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Also update union octeon_cvmemctl with new OCTEON II fields.

[aleksey.makarov@auriga.com: use __BITFIELD_FIELD]
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8940/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Disable ICache prefetch for certian Octeon II processors.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8938/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Commit 2c952e06 ("MIPS: Move cop2 save/restore to switch_to()")
removes assembler code to store COP2 registers.  Commit
a36d8225 ("MIPS: OCTEON: Enable use of FPU") mistakenly
restores it

Fixes: a36d8225 ("MIPS: OCTEON: Enable use of FPU")
Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/8937/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Use dmfc0/dmtc0 instructions for reading CvmMemCtl COP0 register,
its a 64-bit wide.
Signed-off-by: NChandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/8936/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Allocate new save space, and then save/restore the registers if
OCTEON III.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8935/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

It wasn't being saved on task switch.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8934/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The wide multiplier is twice as wide, so we need to save twice as much
state.  Detect the multiplier type (CPU type) at start up and install
model specific handlers.

[aleksey.makarov@auriga.com:
	conflict resolution,
	support for old compilers]
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NLeonid Rosenboim <lrosenboim@caviumnetworks.com>
Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8933/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Allow more compression algorithms as well as uncompressed uImage.bin
to be generated. An uncompressed image might be useful to rule out
problems in the decompression code in the bootloader or even speed
up the boot process at the expense of a bigger uImage file.
Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9271/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8737/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

There are currently no gio device drivers that implement suspend/resume
and this patch removes the bus specific legacy suspend and resume callbacks.
This will allow us to eventually remove struct bus_type legacy suspend and
resume support altogether.

gio device drivers wanting to implement suspend and resume can use dev PM
ops which will work out of the box without further modifications necessary.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Acked-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8920/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Without these, there are multiple definitions of pci_proc_domain()
and pci_domain_nr() if linux/pci.h and asm/pci.h are included.

Add #ifdefs around them
Signed-off-by: NZubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: NMarkos Chandras <Markos.Chandras@imgtec.com>
Cc: Markos.Chandras@imgtec.com
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8670/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The current code uses bits 0-6 of the sys_cpupll register to calculate
core clock speed.  However this is only valid on Au1300, on all earlier
models the hardware only uses bits 0-5 to generate core clock.

This fixes clock calculation on the MTX1 (Au1500), where bit 6 of cpupll
is set as well, which ultimately lead the code to calculate a bogus cpu
core clock and also uart base clock down the line.
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
Reported-by: NJohn Crispin <blogic@openwrt.org>
Tested-by: NBruno Randolf <br1@einfach.org>
Cc: stable@vger.kernel.org	[v3.17+]
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9279/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

set_cpuspec() has been dropped with commit 074cf656
("MIPS: Alchemy: remove cpu_table.") in late 2008.
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9150/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This was lost during the rewrite of clock framework support.
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9149/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The Au1000 and Au1500 calculate the LRCLK a bit differently than
newer models: a single bit in MEM_STCFG0 selects if pclk is divided
by 4 or 5.
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9148/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Build set and clear macros for the PageGrain register.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9289/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

* Clean up white spaces and tabs.
   * Get rid of remaining hardcoded values for calculating
     shifts and masks.
   * Get rid of redundant macro values.
   * Do not use page table bits directly in #ifdef's.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9287/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Export the _save_msa asm function used by the lose_fpu(1) macro to GPL
modules so that KVM can make use of it when it is built as a module.

This fixes the following build error when CONFIG_KVM=m and
CONFIG_CPU_HAS_MSA=y due to commit f798217d ("KVM: MIPS: Don't leak
FPU/DSP to guest"):

ERROR: "_save_msa" [arch/mips/kvm/kvm.ko] undefined!

Fixes: f798217d (KVM: MIPS: Don't leak FPU/DSP to guest)
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 3.15+
Patchwork: https://patchwork.linux-mips.org/patch/9261/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>