1. 22 10月, 2013 10 次提交
  2. 27 9月, 2013 1 次提交
  3. 26 9月, 2013 5 次提交
  4. 25 8月, 2013 1 次提交
  5. 27 6月, 2013 2 次提交
  6. 31 5月, 2013 1 次提交
  7. 27 5月, 2013 2 次提交
    • L
      mmc: sdhci-esdhc-imx: fix multiblock reads on i.MX53 · 361b8482
      Lucas Stach 提交于
      The eSDHC controller on the i.MX53 needs an additional, non spec
      compliant CMD12 after a multiblock read with a predefined number of
      blocks. Otherwise the internal state machine won't go back to the
      idle state.
      
      This commit effectively reverts 5b6b0ad6 (mmc: sdhci-esdhc-imx:
      fix for mmc cards on i.MX5), which fixed part of the problem by
      making multiblock reads work, however this fix was not sufficient
      when multi- and singleblock reads got intermixed.
      
      This implements the recommended workaround (Freescale i.MX Reference
      Manual, section 29.6.8 "Multi-block Read") by manually sending a
      CMD12 with the RSPTYP bits cleared.
      Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      361b8482
    • M
      mmc: sdhci-esdhc-imx: Fix SDIO interrupts · f6825748
      Martin Fuzzey 提交于
      Currently SDIO interrupts do not work on i.MX53 and maybe others.
      
      This was observed with a Marvell 8787 based SDIO wifi adapter
      using the mwifiex driver and firmware from the Marvell git
      repository.
      The symptom was a timeout after firmware download.
      
      Observing the SDIO_DAT1 line showed that an interrupt was requested
      (level 0) but no interrupt was generated in software, the line
      stayed low until a timeout ocurred and the card was reset.
      
      There is a Freescale errata
      	ENGcm11186 "eSDHC misses SDIO interrupt when CINT is disabled"
      
      The workaround suggested by this errata is already implemented and
      involves clearing and then setting the D3CD bit in the host control
      register [see esdhc_writel_le()]
      
      However, when esdhc_writeb_le() is later used to write to
      SDHCI_HOST_CONTROL it always resets the D3CD bit.
      
      To fix this simply add the D3CD bit to the set of bits
      not modified by esdhc_writeb_le().
      Signed-off-by: NMartin Fuzzey <mfuzzey@parkeon.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      f6825748
  8. 23 3月, 2013 2 次提交
  9. 25 2月, 2013 9 次提交
  10. 12 2月, 2013 2 次提交
  11. 28 1月, 2013 2 次提交
  12. 07 12月, 2012 1 次提交
  13. 29 11月, 2012 2 次提交