This patch adds pin definitiones for the MSM8x74 TLMM.
New definitions include:

BLSP devices (I2C, UART, SPI, and UIM), mi2s, gp clk,
pdm, gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif,
sdc3, sdc4, and other assorted pins.
Signed-off-by: NAndy Gross <agross@codeaurora.org>
Acked-By: NBjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Drop underscore in spdif_groups to match all other groups.
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Reviewed-by: NAndy Gross <agross@codeaurora.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This rewrites the SIRF pinctrl driver to allocate a state container
for the GPIO chip, just as is done for the pin controller, and
use the gpiochip_add_pin_range() to add the range from the gpiochip
side rather than adding the range from the pinctrl side.

All resulting changes are done in order to pass around a state
container rather than refer to a static global object.
Acked-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add "power-source" property to generic options used for DT parsing files.
This  enables drivers, which use generic pin configurations, to get the
value passed to this property.
Signed-off-by: NIvan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The irq/pin mapping is used to lookup the pin to mux to the irq
function when the irq is enabled. It is created when gpio_to_irq
is called. Creating the mapping during init allows us to map the
interrupts directly from the device tree.

Originally the IRQ to pin mapping was created when gpio_to_irq
was called with a GPIO handle. The mapping in turn is used to mux
the pin into EINT mode.

If the mapping is created during gpio_to_irq, we can't use the
interrupts directly, i.e. through the DT with "interrupts = <&pio A 4>".

Instead we'd have to use "gpios = <&pio A B>", then pass the gpio
through to gpio_to_irq.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This issue was reported by coccicheck using the semantic patch
at scripts/coccinelle/api/memdup.cocci
Signed-off-by: NBenoit Taine <benoit.taine@lip6.fr>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Use devm_ioremap_resource() because devm_request_and_ioremap() is
obsoleted by devm_ioremap_resource().
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Acked-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The patch 7420d2d0: "pinctrl: sirf: switch driver to use gpiolib
irqchip helpers" from Apr 15, 2014, leads to the following static
checker warning:

      drivers/pinctrl/sirf/pinctrl-sirf.c:578 sirfsoc_gpio_handle_irq()
      warn: buffer overflow 'sgpio_chip.sgpio_bank' 5 <= 31

Cc: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The A31 R_PIO driver depends on the reset framework in a mandatory way. Express
this by adding a depends on the reset framework in Kconfig
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The pin numbers passed to sunxi_*_reg helpers to get the correct
registers should be the pin offset for the PIO block, not the
absolute number we use that is based on the alphanumeric labels
Allwinner uses.

This patch subtracts .pin_base from the pin number passed to these
functions, so the driver accesses the correct registers.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Reviewed-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core
driver.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

With commit 80cc3732 (pinctrl/at91: convert driver to use gpiolib irqchip)
gpiochip_set_chained_irqchip is called for PIOC, PIOD and PIOE. The
associated GPIO chip for the IRQ chip is overwritten each time, because
they share the same hard IRQ line.
Thus if an IRQ occurs on PIOC or PIOD, gpio_irq_handler will only check on
PIOE (the assigned GPIO chip) where no event occured. Thus the IRQ will
not be cleared, retriggering the ISR.
Fix that (like done before) by only set the PIOC GPIO chip to the IRQ chip
and walk the list in the irq handler.
Signed-off-by: NAlexander Stein <alexanders83@web.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This switches the Qualcomm MSM pin control driver over to using
the generic GPIO irqchip helpers.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Josh Cartwright <joshc@codeaurora.org>
Acked-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

When the support for the PRCM muxer on the A31 has been added, the global
static pinctl_desc definition has been left as is. Unfortunately, this
structure is used to register the pinctrl device, and prior to this
registration, we set the name and pins field.

Since this structure is shared across instances, that means that the latest
registered pinctrl device wins in setting the name, pins and pins numbers,
which is not really a good thing.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Fix the following configuration error:
drivers/pinctrl/sunxi/Kconfig:3:error: recursive dependency detected!
drivers/pinctrl/sunxi/Kconfig:3:	symbol PINCTRL_SUNXI is selected by PINCTRL_SUN4I_A10
drivers/pinctrl/sunxi/Kconfig:9:	symbol PINCTRL_SUN4I_A10 default value contains PINCTRL_SUNXI

Add a new intermedia PINCTRL_SUNXI_COMMON, that superseeds the PINCTRL_SUNXI
one.

We still need to keep PINCTRL_SUNXI at the moment in order to preserve
bisectability. Indeed, during that merge window, we also introduced the
MACH_SUN* symbols. Since it's going through different trees, we can't rely on
the fact that the options will be there, while ARCH_SUNXI still select
PINCTRL_SUNXI.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Suggested-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the pin-controller driver for the Berlin BG2Q SoC, with definition
of its groups and functions. Pin control registers are part of chip/
system control registers, which will be represented by a single node.
Until a proper driver for the chip/system control is available,
register the corresponding regmap in pinctrl driver probe.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the pin-controller driver for the Berlin BG2 SoC, with definition
of its groups and functions. Pin control registers are part of chip/
system control registers, which will be represented by a single node.
Until a proper driver for the chip/system control is available,
register the corresponding regmap in pinctrl driver probe.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the pin-controller driver for the Berlin BG2Q SoC, with definition
of its groups and functions. Pin control registers are part of chip/
system control registers, which will be represented by a single node.
Until a proper driver for the chip/system control is available,
register the corresponding regmap in pinctrl driver probe.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The Marvell Berlin boards have a group based pinmuxing mechanism. This
adds the core driver support. We actually do not need any information
about the pins here and only have the definition of the groups.

Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and
BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set
to mode 0:

Group	Modes	Offset Base	Offset	LSB	Bit Width
GSM12	3	sm_base		0x40	0x10	0x2

Ball	Group	Mode 0		Mode 1		Mode 2
BK4	GSM12	UART0_RX	IrDA0_RX	GPIO9
BH6	GSM12	UART0_TX	IrDA0_TX	GPIO10

So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need
to set (sm_base + 0x40 + 0x10) &= ff3fffff.

As pin control registers are part of either chip control or system
control registers, that deal with a bunch of other functions we rely
on a regmap instead of exclusively remapping any resources.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In case of resolving power management or similar issues it might be useful
to have these properties included in the debugfs output.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: NMathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

If chip->to_irq is NULL ACPI GPIO helpers don't register GPIO event
handlers thus preventing any ACPI GPIO triggered events. Solve this by
calling gpiochip_add() after we have set up drivers chip->to_irq hook.
Signed-off-by: NJin Yao <yao.jin@intel.com>
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Now that the x86 dynamic IRQ allocation problem has been resolved with
commmit 62a08ae2 (genirq: x86: Ensure that dynamic irq allocation does
not conflict), we can add back Baytrail-T ACPI ID to the pinctrl driver.

This makes the driver to work on Asus T100 where it is needed for several
things like ACPI GPIO events and SD card detection.

References: https://bugzilla.kernel.org/show_bug.cgi?id=68291Acked-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: NJin Yao <yao.jin@intel.com>
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add #ifdefs to allow r8a73a4 Multiplatform build. Needed
to enable r8a73a4 Multiplatform support.
Signed-off-by: NMagnus Damm <damm+renesas@opensource.se>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add #ifdefs to allow sh73a0 Multiplatform build. Needed
to enable sh73a0 Multiplatform support.
Signed-off-by: NMagnus Damm <damm+renesas@opensource.se>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add #ifdefs to allow r8a7740 Multiplatform build. Needed
to enable r8a7740 Multiplatform support.
Signed-off-by: NMagnus Damm <damm+renesas@opensource.se>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In the multiplatform kernel case the IRQs associated with the PFC GPIOs
are specified through DT. The pinmux_irq irq field is thus ignored by
the code, and doesn't need to be set.

This will allow removing the mach/irq.h include from pfc-*.c files that
was required for the irq_pin() macro used to initialize the irq field.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Enable the freshly introduced Kconfig options whenever their matching
architecture is enabled.

Since the Kconfig symbols for these machines are going through a different
tree, keep PINCTRL_SUNXI around for the moment to avoid breaking the defconfig.
It should be removed eventually.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Introduce the syscons for grf and pmu and deprecate the previous register
areas.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NMax Schwarz <max.schwarz@online.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This allows the basic registers of the general register files to be supplied
by a syscon instead of being mapped locally.

The GRF registers contain a lot more than pinctrl functions like dma, usb-phy
and general soc control and status registers, intermixed with the iomux, pull
and drive-strength registers.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NMax Schwarz <max.schwarz@online.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

When the pmu registers are supplied through a syscon regmap we do not need
to map the registers ourself.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NMax Schwarz <max.schwarz@online.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Currently the pmu registers containing pin pull settings on the rk3188 are mapped
locally when bank0 is instantiated. Add an alternative that can resolve the pmu
from a syscon phandle.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NMax Schwarz <max.schwarz@online.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Convert rockchip_get_bank_data to use the struct rockchip_pinctrl because
later on we need to check a value from it when registering the gpio banks.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NMax Schwarz <max.schwarz@online.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This allows us to use syscons in the future.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NMax Schwarz <max.schwarz@online.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Deprecate secondary register area for rk3188 pulls. Instead use big enough
initial mapping of grf registers to catch all.

The now deprecated register is still supported though.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NMax Schwarz <max.schwarz@online.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Pinctrl cleanup and reworks for 3.16

This serie of patch:
  - Moves the Allwinner pinctrl driver to a folder of its own
  - removes the sunxi-pinctrl-pins header, and split the driver into a core
    one, with all the logic, and smaller drivers, one for each SoC, that
    declare the pins, and will provide to the core the set of pins.
  - And does a few cleanups here and there.

The way that reset is handled right now is that it is made optional for every
pinctrl driver, while actually, it isn't used at all for the main pin
controllers so far, and while it's mandatory for the A31's secondary pin
controller.

Move the reset functions out of the core and in the driver, where they can be
made mandatory.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add one Kconfig option for each driver. This will allow to better control which
driver is enabled, instead of having either all or nothing.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Move the pin description to a driver specific to be.

This is the final step toward retiring pinctrl-sunxi-pins.h that used to define
all the pins for all the Allwinner SoCs in a single header, that would have in
turn result in having these structures in the final binary as many times as the
header was included.

We can finally remove that header, and remove all the driver part of the
pinctrl-sunxi core.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>