1. 23 3月, 2011 1 次提交
  2. 11 3月, 2011 1 次提交
  3. 24 2月, 2011 1 次提交
    • S
      x86: Add device tree support · da6b737b
      Sebastian Andrzej Siewior 提交于
      This patch adds minimal support for device tree on x86. The device
      tree blob is passed to the kernel via setup_data which requires at
      least boot protocol 2.09.
      
      Memory size, restricted memory regions, boot arguments are gathered
      the traditional way so things like cmd_line are just here to let the
      code compile.
      
      The current plan is use the device tree as an extension and to gather
      information which can not be enumerated and would have to be hardcoded
      otherwise. This includes things like 
         - which devices are on this I2C/SPI bus?
         - how are the interrupts wired to IO APIC?
         - where could my hpet be?
      Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
      Signed-off-by: NDirk Brandewie <dirk.brandewie@gmail.com>
      Acked-by: NGrant Likely <grant.likely@secretlab.ca>
      Cc: sodaville@linutronix.de
      Cc: devicetree-discuss@lists.ozlabs.org
      LKML-Reference: <1298405266-1624-3-git-send-email-bigeasy@linutronix.de>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      da6b737b
  4. 18 2月, 2011 2 次提交
    • H
      x86, reboot: Move the real-mode reboot code to an assembly file · 3d35ac34
      H. Peter Anvin 提交于
      Move the real-mode reboot code out to an assembly file (reboot_32.S)
      which is allocated using the common lowmem trampoline allocator.
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      LKML-Reference: <4D5DFBE4.7090104@intel.com>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      Cc: Rafael J. Wysocki <rjw@sisk.pl>
      Cc: Matthieu Castet <castet.matthieu@free.fr>
      3d35ac34
    • H
      x86, trampoline: Common infrastructure for low memory trampolines · 4822b7fc
      H. Peter Anvin 提交于
      Common infrastructure for low memory trampolines.  This code installs
      the trampolines permanently in low memory very early.  It also permits
      multiple pieces of code to be used for this purpose.
      
      This code also introduces a standard infrastructure for computing
      symbol addresses in the trampoline code.
      
      The only change to the actual SMP trampolines themselves is that the
      64-bit trampoline has been made reusable -- the previous version would
      overwrite the code with a status variable; this moves the status
      variable to a separate location.
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      LKML-Reference: <4D5DFBE4.7090104@intel.com>
      Cc: Rafael J. Wysocki <rjw@sisk.pl>
      Cc: Matthieu Castet <castet.matthieu@free.fr>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      4822b7fc
  5. 18 12月, 2010 1 次提交
  6. 07 12月, 2010 1 次提交
  7. 20 11月, 2010 1 次提交
  8. 18 11月, 2010 1 次提交
  9. 27 10月, 2010 7 次提交
  10. 19 10月, 2010 1 次提交
    • P
      irq_work: Add generic hardirq context callbacks · e360adbe
      Peter Zijlstra 提交于
      Provide a mechanism that allows running code in IRQ context. It is
      most useful for NMI code that needs to interact with the rest of the
      system -- like wakeup a task to drain buffers.
      
      Perf currently has such a mechanism, so extract that and provide it as
      a generic feature, independent of perf so that others may also
      benefit.
      
      The IRQ context callback is generated through self-IPIs where
      possible, or on architectures like powerpc the decrementer (the
      built-in timer facility) is set to generate an interrupt immediately.
      
      Architectures that don't have anything like this get to do with a
      callback from the timer tick. These architectures can call
      irq_work_run() at the tail of any IRQ handlers that might enqueue such
      work (like the perf IRQ handler) to avoid undue latencies in
      processing the work.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Acked-by: NKyle McMartin <kyle@mcmartin.ca>
      Acked-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
      [ various fixes ]
      Signed-off-by: NHuang Ying <ying.huang@intel.com>
      LKML-Reference: <1287036094.7768.291.camel@yhuang-dev>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      e360adbe
  11. 16 10月, 2010 1 次提交
  12. 13 10月, 2010 1 次提交
    • D
      x86, olpc: Add XO-1 poweroff support · bf1ebf00
      Daniel Drake 提交于
      Add a pm_power_off handler for the OLPC XO-1 laptop.
      
      The driver can be built modular and follows the behaviour of the
      APM driver, setting pm_power_off to NULL on unload. However, the
      ability to unload the module will probably be removed (with a simple
      __module_get(THIS_MODULE)) if/when XO-1 suspend/resume support is
      added to this file at a later date.
      Signed-off-by: NDaniel Drake <dsd@laptop.org>
      LKML-Reference: <20101010094032.9AE669D401B@zog.reactivated.net>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      bf1ebf00
  13. 08 10月, 2010 1 次提交
    • F
      x86, earlyprintk: Add earlyprintk for Intel Moorestown platform · c20b5c33
      Feng Tang 提交于
      Intel Moorestown platform has a spi-uart device(Maxim3110),
      which connects to a Designware spi core controller. This patch
      will add early console function based on it.
      
      As it will be used long before Linux spi subsystem get
      initialised, we simply directly manipulate the spi controller's
      register to acheive the early console func. This is safe as it
      will be disabled when devices subsytem get initialised.
      
      To use it, user need enable CONFIG_X86_MRST_EARLY_PRINTK in
      kenrel config and add "earlyprintk=mrst" in kernel command line.
      Signed-off-by: NFeng Tang <feng.tang@intel.com>
      Acked-by: NAlan Cox <alan@linux.intel.com>
      Cc: greg@kroah.com
      LKML-Reference: <1284361736-23011-4-git-send-email-feng.tang@intel.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c20b5c33
  14. 23 9月, 2010 3 次提交
  15. 21 9月, 2010 1 次提交
  16. 27 8月, 2010 1 次提交
    • K
      x86, iommu: Add proper dependency sort routine (and sanity check). · 5bef80a4
      Konrad Rzeszutek Wilk 提交于
      We are using a very simple sort routine which sorts the .iommu_table
      array in the order of dependencies. Specifically each structure
      of iommu_table_entry has a field 'depend' which contains the function
      pointer to the IOMMU that MUST be run before us. We sort the array
      of structures so that the struct iommu_table_entry with no
      'depend' field are first, and then the subsequent ones are the
      ones for which the 'depend' function has been already invoked
      (in other words, precede us).
      
      Using the kernel's version 'sort', which is a mergeheap is
      feasible, but would require making the comparison operator
      scan recursivly the array to satisfy the "heapify" process: setting the
      levels properly. The end result would much more complex than it should
      be an it is just much simpler to utilize this simple sort routine.
      Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      LKML-Reference: <1282845485-8991-4-git-send-email-konrad.wilk@oracle.com>
      CC: H. Peter Anvin <hpa@zytor.com>
      CC: Fujita Tomonori <fujita.tomonori@lab.ntt.co.jp>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      5bef80a4
  17. 24 8月, 2010 1 次提交
    • A
      x86, vmware: Remove deprecated VMI kernel support · 9863c90f
      Alok Kataria 提交于
      With the recent innovations in CPU hardware acceleration technologies
      from Intel and AMD, VMware ran a few experiments to compare these
      techniques to guest paravirtualization technique on VMware's platform.
      These hardware assisted virtualization techniques have outperformed the
      performance benefits provided by VMI in most of the workloads. VMware
      expects that these hardware features will be ubiquitous in a couple of
      years, as a result, VMware has started a phased retirement of this
      feature from the hypervisor.
      
      Please note that VMI has always been an optimization and non-VMI kernels
      still work fine on VMware's platform.
      Latest versions of VMware's product which support VMI are,
      Workstation 7.0 and VSphere 4.0 on ESX side, future maintainence
      releases for these products will continue supporting VMI.
      
      For more details about VMI retirement take a look at this,
      http://blogs.vmware.com/guestosguide/2009/09/vmi-retirement.html
      
      This feature removal was scheduled for 2.6.37 back in September 2009.
      Signed-off-by: NAlok N Kataria <akataria@vmware.com>
      LKML-Reference: <1282600151.19396.22.camel@ank32.eng.vmware.com>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      9863c90f
  18. 19 6月, 2010 1 次提交
    • A
      x86, olpc: Add support for calling into OpenFirmware · fd699c76
      Andres Salomon 提交于
      Add support for saving OFW's cif, and later calling into it to run OFW
      commands.  OFW remains resident in memory, living within virtual range
      0xff800000 - 0xffc00000.  A single page directory entry points to the
      pgdir that OFW actually uses, so rather than saving the entire page
      table, we grab and install that one entry permanently in the kernel's
      page table.
      
      This is currently only used by the OLPC XO.  Note that this particular
      calling convention breaks PAE and PAT, and so cannot be used on newer
      x86 hardware.
      Signed-off-by: NAndres Salomon <dilinger@queued.net>
      LKML-Reference: <20100618174653.7755a39a@dev.queued.net>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      fd699c76
  19. 26 3月, 2010 1 次提交
    • P
      x86, perf, bts, mm: Delete the never used BTS-ptrace code · faa4602e
      Peter Zijlstra 提交于
      Support for the PMU's BTS features has been upstreamed in
      v2.6.32, but we still have the old and disabled ptrace-BTS,
      as Linus noticed it not so long ago.
      
      It's buggy: TIF_DEBUGCTLMSR is trampling all over that MSR without
      regard for other uses (perf) and doesn't provide the flexibility
      needed for perf either.
      
      Its users are ptrace-block-step and ptrace-bts, since ptrace-bts
      was never used and ptrace-block-step can be implemented using a
      much simpler approach.
      
      So axe all 3000 lines of it. That includes the *locked_memory*()
      APIs in mm/mlock.c as well.
      Reported-by: NLinus Torvalds <torvalds@linux-foundation.org>
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Roland McGrath <roland@redhat.com>
      Cc: Oleg Nesterov <oleg@redhat.com>
      Cc: Markus Metzger <markus.t.metzger@intel.com>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      LKML-Reference: <20100325135413.938004390@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      faa4602e
  20. 25 2月, 2010 1 次提交
    • J
      x86, apbt: Moorestown APB system timer driver · bb24c471
      Jacob Pan 提交于
      Moorestown platform does not have PIT or HPET platform timers.  Instead it
      has a bank of eight APB timers.  The number of available timers to the os
      is exposed via SFI mtmr tables.  All APB timer interrupts are routed via
      ioapic rtes and delivered as MSI.
      Currently, we use timer 0 and 1 for per cpu clockevent devices, timer 2
      for clocksource.
      Signed-off-by: NJacob Pan <jacob.jun.pan@intel.com>
      LKML-Reference: <43F901BD926A4E43B106BF17856F0755A318D2D2@orsmsx508.amr.corp.intel.com>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      bb24c471
  21. 17 2月, 2010 1 次提交
  22. 13 2月, 2010 1 次提交
  23. 16 12月, 2009 1 次提交
  24. 31 8月, 2009 2 次提交
  25. 29 8月, 2009 1 次提交
  26. 27 8月, 2009 1 次提交
    • T
      x86: Add x86_init infrastructure · 57844a8f
      Thomas Gleixner 提交于
      The upcoming Moorestown support brings the embedded world to x86. The
      setup code of x86 has already a couple of hooks which are either
      x86_quirks or paravirt ops. Some of those setup hooks are pretty
      convoluted like the timer setup and the tsc calibration code. But
      there are other places which could do with a cleanup.
      
      Instead of having inline functions/macros which are modified at
      compile time I decided to introduce x86_init ops which are
      unconditional in the code and make it clear that they can be changed
      either during compile time or in the early boot process. The function
      pointers are initialized by default functions which can be noops so
      that the pointer can be called unconditionally in the most cases. This
      also allows us to remove 32bit/64bit, paravirt and other #ifdeffery.
      
      paravirt guests are just a hardware platform in the setup code, so we
      should treat them as such and not hide all behind multiple layers of
      indirection and compile time dependencies.
      
      It's more obvious that x86_init.timers.timer_init() is a function
      pointer than the late_time_init = choose_time_init() obscurity. It's
      also way simpler to grep for x86_init.timers.timer_init and find all
      the places which modify that function pointer instead of analyzing
      weak functions, macros and paravirt indirections.
      
      Note. This is not a general paravirt_ops replacement. It just will
      move setup related hooks which are potentially useful for other
      platform setup purposes as well out of the paravirt domain.
      
      Add the base infrastructure without any functionality.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      57844a8f
  27. 22 7月, 2009 1 次提交
    • J
      x86, intel_txt: Intel TXT boot support · 31625340
      Joseph Cihula 提交于
      This patch adds kernel configuration and boot support for Intel Trusted
      Execution Technology (Intel TXT).
      
      Intel's technology for safer computing, Intel Trusted Execution
      Technology (Intel TXT), defines platform-level enhancements that
      provide the building blocks for creating trusted platforms.
      
      Intel TXT was formerly known by the code name LaGrande Technology (LT).
      
      Intel TXT in Brief:
      o  Provides dynamic root of trust for measurement (DRTM)
      o  Data protection in case of improper shutdown
      o  Measurement and verification of launched environment
      
      Intel TXT is part of the vPro(TM) brand and is also available some
      non-vPro systems.  It is currently available on desktop systems based on
      the Q35, X38, Q45, and Q43 Express chipsets (e.g. Dell Optiplex 755, HP
      dc7800, etc.) and mobile systems based on the GM45, PM45, and GS45
      Express chipsets.
      
      For more information, see http://www.intel.com/technology/security/.
      This site also has a link to the Intel TXT MLE Developers Manual, which
      has been updated for the new released platforms.
      
      A much more complete description of how these patches support TXT, how to
      configure a system for it, etc. is in the Documentation/intel_txt.txt file
      in this patch.
      
      This patch provides the TXT support routines for complete functionality,
      documentation for TXT support and for the changes to the boot_params structure,
      and boot detection of a TXT launch.  Attempts to shutdown (reboot, Sx) the system
      will result in platform resets; subsequent patches will support these shutdown modes
      properly.
      
       Documentation/intel_txt.txt      |  210 +++++++++++++++++++++
       Documentation/x86/zero-page.txt  |    1
       arch/x86/include/asm/bootparam.h |    3
       arch/x86/include/asm/fixmap.h    |    3
       arch/x86/include/asm/tboot.h     |  197 ++++++++++++++++++++
       arch/x86/kernel/Makefile         |    1
       arch/x86/kernel/setup.c          |    4
       arch/x86/kernel/tboot.c          |  379 +++++++++++++++++++++++++++++++++++++++
       security/Kconfig                 |   30 +++
       9 files changed, 827 insertions(+), 1 deletion(-)
      Signed-off-by: NJoseph Cihula <joseph.cihula@intel.com>
      Signed-off-by: NShane Wang <shane.wang@intel.com>
      Signed-off-by: NGang Wei <gang.wei@intel.com>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      31625340
  28. 07 7月, 2009 1 次提交
  29. 19 6月, 2009 1 次提交
    • P
      gcov: enable GCOV_PROFILE_ALL for x86_64 · 7bf99fb6
      Peter Oberparleiter 提交于
      Enable gcov profiling of the entire kernel on x86_64. Required changes
      include disabling profiling for:
      
      * arch/kernel/acpi/realmode and arch/kernel/boot/compressed:
        not linked to main kernel
      * arch/vdso, arch/kernel/vsyscall_64 and arch/kernel/hpet:
        profiling causes segfaults during boot (incompatible context)
      Signed-off-by: NPeter Oberparleiter <oberpar@linux.vnet.ibm.com>
      Cc: Andi Kleen <andi@firstfloor.org>
      Cc: Huang Ying <ying.huang@intel.com>
      Cc: Li Wei <W.Li@Sun.COM>
      Cc: Michael Ellerman <michaele@au1.ibm.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Heiko Carstens <heicars2@linux.vnet.ibm.com>
      Cc: Martin Schwidefsky <mschwid2@linux.vnet.ibm.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: WANG Cong <xiyou.wangcong@gmail.com>
      Cc: Sam Ravnborg <sam@ravnborg.org>
      Cc: Jeff Dike <jdike@addtoit.com>
      Cc: Al Viro <viro@zeniv.linux.org.uk>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      7bf99fb6
  30. 12 6月, 2009 1 次提交