1. 04 12月, 2006 14 次提交
  2. 22 11月, 2006 1 次提交
  3. 13 11月, 2006 5 次提交
  4. 10 11月, 2006 1 次提交
    • J
      [POWERPC] pseries: Force 4k update_flash block and list sizes · ae883cab
      John Rose 提交于
      The enablement of 64k pages on pseries platforms exposed a bug in
      the RTAS mechanism for updating firmware.  RTAS assumes 4k for flash
      block and list sizes, and use of any other sizes results in a failure,
      even though PAPR does not specify any such requirement.
      
      This patch changes the rtas_flash module to force the use of 4k memory
      block and list sizes when preparing and sending a firmware image to
      RTAS.  The rtas_flash function now uses a slab cache of 4k blocks with
      4k alignment, rather than get_zeroed_page(), to allocate the memory for
      the flash blocks and lists.  The 4k alignment requirement is specified
      in PAPR.
      Signed-off-by: NJohn Rose <johnrose@austin.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      ae883cab
  5. 02 11月, 2006 1 次提交
  6. 01 11月, 2006 4 次提交
    • B
      [POWERPC] Make alignment exception always check exception table · 4393c4f6
      Benjamin Herrenschmidt 提交于
      The alignment exception used to only check the exception table for
      -EFAULT, not for other errors. That opens an oops window if we can
      coerce the kernel into getting an alignment exception for other reasons
      in what would normally be a user-protected accessor, which can be done
      via some of the futex ops. This fixes it by always checking the
      exception tables.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      4393c4f6
    • L
      [POWERPC] Use 4kB iommu pages even on 64kB-page systems · 5d2efba6
      Linas Vepstas 提交于
      The 10Gigabit ethernet device drivers appear to be able to chew
      up all 256MB of TCE mappings on pSeries systems, as evidenced by
      numerous error messages:
      
       iommu_alloc failed, tbl c0000000010d5c48 vaddr c0000000d875eff0 npages 1
      
      Some experimentation indicates that this is essentially because
      one 1500 byte ethernet MTU gets mapped as a 64K DMA region when
      the large 64K pages are enabled. Thus, it doesn't take much to
      exhaust all of the available DMA mappings for a high-speed card.
      
      This patch changes the iommu allocator to work with its own
      unique, distinct page size. Although the patch is long, its
      actually quite simple: it just #defines a distinct IOMMU_PAGE_SIZE
      and then uses this in all the places that matter.
      
      As a side effect, it also dramatically improves network performance
      on platforms with H-calls on iommu translation inserts/removes (since
      we no longer call it 16 times for a 1500 bytes packet when the iommu HW
      is still 4k).
      
      In the future, we might want to make the IOMMU_PAGE_SIZE a variable
      in the iommu_table instance, thus allowing support for different HW
      page sizes in the iommu itself.
      Signed-off-by: NLinas Vepstas <linas@austin.ibm.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Acked-by: NOlof Johansson <olof@lixom.net>
      Acked-by: NStephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      5d2efba6
    • A
      [POWERPC] Fix oprofile support for e500 in arch/powerpc · dd6c89f6
      Andy Fleming 提交于
      Fixed a compile error in building the 85xx support with oprofile, and in
      the process cleaned up some issues with the fsl_booke performance monitor
      code.
      
      * Reorganized FSL Book-E performance monitoring code so that the 7450
        wouldn't be built if the e500 was, and cleaned it up so it was more
        self-contained.
      
      * Added a cpu_setup function for FSL Book-E.  The original
        cpu_setup function prototype had no arguments, assuming that
        the reg_setup function would copy the required information into
        variables which represented the registers.  This was silly for
        e500, since it has 1 register per counter (rather than 3 for
        all counters), so the code has been restructured to have
        cpu_setup take the current counter config array as an argument,
        with op_powerpc_setup() invoking op_powerpc_cpu_setup() through
        on_each_cpu(), and op_powerpc_cpu_setup() invoking the
        model-specific cpu_setup function with an argument.  The
        argument is ignored on all other platforms at present.
      
      * Fixed a confusing line where a trinary operator only had two
        arguments
      Signed-off-by: NAndrew Fleming <afleming@freescale.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      dd6c89f6
    • B
      [POWERPC] Fix various offb issues · 441cbd8d
      Benjamin Herrenschmidt 提交于
      This patch fixes a few issues in offb:
      
       - A test was inverted causing the palette hack to never work
      (no device node was passed down to the init function)
      
       - Some cards seem to have their assigned-addresses property in a random
      order, thus we need to try using of_get_pci_address() first, which will
      fail if it's not a PCI device, and fallback to of_get_address() in that
      case. of_get_pci_address() properly parsees assigned-addresses to test
      the BAR number and thus will get it right whatever the order is.
      
       - Some cards (like GXT4500) provide a linebytes of 0xffffffff in the
      device-tree which does no good. This patch handles that by using the
      screen width when that happens. (Also fixes btext.c while at it).
      
       - Add detection of the GXT4500 in addition to the GXT2000 for the
      palette hacks (we use the same hack, palette is linear in register space
      at offset 0x6000).
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      441cbd8d
  7. 28 10月, 2006 1 次提交
  8. 26 10月, 2006 1 次提交
  9. 25 10月, 2006 9 次提交
  10. 24 10月, 2006 1 次提交
  11. 23 10月, 2006 2 次提交
    • J
      [POWERPC] Add 970GX cputable entry · 362ff7b2
      Jake Moilanen 提交于
      970GX cputable entry from Steve Winiecki.
      Signed-off-by: NJake Moilanen <moilanen@austin.ibm.com>
      
       arch/powerpc/kernel/cputable.c          |   15 +++++++++++++++
       arch/powerpc/oprofile/op_model_power4.c |    2 +-
       include/asm-powerpc/reg.h               |    1 +
       3 files changed, 17 insertions(+), 1 deletion(-)
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      362ff7b2
    • S
      [POWERPC] Simplify stolen time calculation · cbcdb93d
      Stephen Rothwell 提交于
      In calculating stolen time, we were trying to actually account for time
      spent in the hypervisor.  We don't really have enough information to do
      that accurately, so don't try.  Instead, we now calculate stolen time as
      time that the current cpu thread is not actually dispatching instructions.
      On chips without a PURR, we cannot do this, so stolen time will always
      be zero.  On chips with a PURR, this is merely the difference between
      the elapsed PURR values and the elapsed TB values.
      
      This gives us much more sane vaules from tools such as mpstat, even if
      they are still a bit strange e.g. 2 busy threads on one cpu will both
      appear to have 50% user time and 50% stolen time while 1 busy thread on
      a cpu will look like 100% user on one of them and 100% idle on the other.
      Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      cbcdb93d