This PCI host bridge from V3 Semiconductor needs no further
introduction. An ancient driver for it has been sitting in
arch/arm/mach-integrator/pci_v3.* since before v2.6.12 and the
initial migration to git.

But we need to get the drivers out of arch/arm/* and get proper handling of
the old drivers, rewrite and clean up so the PCI maintainer can control the
mass of drivers without having to run all over the kernel. We also switch
swiftly to all the new infrastructure found in the PCI hosts as of late.

Some code is preserved so I have added an extensive list of authors in the
top comment section.

This driver probes with the following result:

  OF: PCI: host bridge /pciv3@62000000 ranges:
  OF: PCI:   No bus range found for /pciv3@62000000, using [bus 00-ff]
  OF: PCI:    IO 0x60000000..0x6000ffff -> 0x00000000
  OF: PCI:   MEM 0x40000000..0x4fffffff -> 0x40000000
  OF: PCI:   MEM 0x50000000..0x5fffffff -> 0x50000000
  pci-v3-semi 62000000.pciv3: initialized PCI V3 Integrator/AP integration
  pci-v3-semi 62000000.pciv3: PCI host bridge to bus 0000:00
  pci_bus 0000:00: root bus resource [bus 00-ff]
  pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
  pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
  pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff pref]
  pci-v3-semi 62000000.pciv3: parity error interrupt
  pci-v3-semi 62000000.pciv3: master abort error interrupt
  pci-v3-semi 62000000.pciv3: PCI target LB->PCI READ abort interrupt
  pci-v3-semi 62000000.pciv3: master abort error interrupt
  (repeats a few times)
  pci 0000:00:09.0: [1011:0024] type 01 class 0x060400
  pci-v3-semi 62000000.pciv3: master abort error interrupt
  pci-v3-semi 62000000.pciv3: PCI target LB->PCI READ abort interrupt
  pci 0000:00:0b.0: [8086:1229] type 00 class 0x020000
  pci 0000:00:0b.0: reg 0x10: [mem 0x00000000-0x00000fff pref]
  pci 0000:00:0b.0: reg 0x14: [io  0x0000-0x001f]
  pci 0000:00:0b.0: reg 0x18: [mem 0x00000000-0x000fffff]
  pci 0000:00:0b.0: reg 0x30: [mem 0x00000000-0x000fffff pref]
  pci 0000:00:0b.0: supports D1 D2
  pci 0000:00:0b.0: PME# supported from D0 D1 D2 D3hot
  pci 0000:00:0c.0: [5333:8811] type 00 class 0x030000
  pci 0000:00:0c.0: reg 0x10: [mem 0x00000000-0x03ffffff]
  pci 0000:00:0c.0: reg 0x30: [mem 0x00000000-0x0000ffff pref]
  pci 0000:00:0c.0: vgaarb: VGA device added: decodes=io+mem,owns=io,locks=none
  PCI: bus0: Fast back to back transfers disabled
  PCI: bus1: Fast back to back transfers enabled
  pci 0000:00:0c.0: BAR 0: assigned [mem 0x40000000-0x43ffffff]
  pci 0000:00:0b.0: BAR 2: assigned [mem 0x44000000-0x440fffff]
  pci 0000:00:0b.0: BAR 6: assigned [mem 0x50000000-0x500fffff pref]
  pci 0000:00:0c.0: BAR 6: assigned [mem 0x50100000-0x5010ffff pref]
  pci 0000:00:0b.0: BAR 0: assigned [mem 0x50110000-0x50110fff pref]
  pci 0000:00:0b.0: BAR 1: assigned [io  0x1000-0x101f]
  pci 0000:00:09.0: PCI bridge to [bus 01]
  pci 0000:00:0b.0: Firmware left e100 interrupts enabled; disabling
  (...)
  e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
  e100: Copyright(c) 1999-2006 Intel Corporation
  e100 0000:00:0b.0: enabling device (0146 -> 0147)
  e100 0000:00:0b.0 eth0: addr 0x50110000, irq 31, MAC addr 00:08:c7:99:d2:57

> lspci
  00:0b.0 Class 0200: 8086:1229
  00:09.0 Class 0604: 1011:0024
  00:0c.0 Class 0300: 5333:8811

> cat /proc/iomem
  40000000-4fffffff : V3 PCI NON-PRE-MEM
    40000000-43ffffff : 0000:00:0c.0
    44000000-440fffff : 0000:00:0b.0
      44000000-440fffff : e100
  50000000-5fffffff : V3 PCI PRE-MEM
    50000000-500fffff : 0000:00:0b.0
    50100000-5010ffff : 0000:00:0c.0
    50110000-50110fff : 0000:00:0b.0
      50110000-50110fff : e100
  61000000-61ffffff : /pciv3@62000000
  62000000-6200ffff : /pciv3@62000000
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
[bhelgaas: fold in %pR fixes from Arnd Bergmann <arnd@arndb.de>:
http://lkml.kernel.org/r/20171011140224.3770968-1-arnd@arndb.de]
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
CC: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>

This driver is required to work around several hardware bugs in the PCIe
controller.

The SMP8759 does not support legacy interrupts or IO space.
Signed-off-by: NMarc Gonzalez <marc_gonzalez@sigmadesigns.com>
[bhelgaas: add CONFIG_BROKEN dependency, various cleanups]
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add support for the MediaTek PCIe Gen2 controller which can be found on
MT7623 series SoCs.

[bhelgaas: fold in mtk_pcie_parse_and_add_res() bugfix from
http://lkml.kernel.org/r/1496644078-27122-1-git-send-email-ryder.lee@mediatek.com]
[bhelgaas: fold in MAINTAINERS update from
http://lkml.kernel.org/r/1497588789-28607-1-git-send-email-ryder.lee@mediatek.com]
[bhelgaas: fold in pci_scan_root_bus_bridge() update and leak fix from
http://lkml.kernel.org/r/1498555451-55073-2-git-send-email-ryder.lee@mediatek.com]
[bhelgaas: fold in powerup fixes from
http://lkml.kernel.org/r/1497866400-41844-2-git-send-email-ryder.lee@mediatek.com]
[bhelgaas: fold in poweroff when link down fixes from
http://lkml.kernel.org/r/1497866400-41844-3-git-send-email-ryder.lee@mediatek.com]
[bhelgaas: fold in optional property fixes from
http://lkml.kernel.org/r/1497866400-41844-4-git-send-email-ryder.lee@mediatek.com]
[bhelgaas: set host->map_irq and host->swizzle_irq and drop
pci_fixup_irqs(), remove unnecessary "return", rename mtk_pcie_link_is_up()
to mtk_pcie_link_up() for consistency, add local struct device pointer]
[bhelgaas: fold in pci_add_flags() removal from
http://lkml.kernel.org/r/1499061300-55951-1-git-send-email-ryder.lee@mediatek.com]
Signed-off-by: NRyder Lee <ryder.lee@mediatek.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add a host bridge driver for the Faraday Technology FPPCI100 host bridge,
used for Cortina Systems Gemini SoC (SL3516) PCI Host Bridge.

This code is inspired by the out-of-tree OpenWRT patch and then extensively
rewritten for device tree and using the modern helpers to cut down and
modernize the code to all new PCI frameworks.  A driver exists in U-Boot as
well.

Tested on the ITian Square One SQ201 NAS with the following result in the
boot log (trimmed to relevant parts):

  OF: PCI: host bridge /soc/pci@50000000 ranges:
  OF: PCI:    IO 0x50000000..0x500fffff -> 0x00000000
  OF: PCI:   MEM 0x58000000..0x5fffffff -> 0x58000000
  ftpci100 50000000.pci: PCI host bridge to bus 0000:00
  pci_bus 0000:00: root bus resource [bus 00-ff]
  pci_bus 0000:00: root bus resource [io  0x0000-0xfffff]
  pci_bus 0000:00: root bus resource [mem 0x58000000-0x5fffffff]
  ftpci100 50000000.pci:
    DMA MEM1 BASE: 0x0000000000000000 -> 0x0000000007ffffff config 00070000
  ftpci100 50000000.pci:
    DMA MEM2 BASE: 0x0000000000000000 -> 0x0000000003ffffff config 00060000
  ftpci100 50000000.pci:
    DMA MEM3 BASE: 0x0000000000000000 -> 0x0000000003ffffff config 00060000
  PCI: bus0: Fast back to back transfers disabled
  pci 0000:00:00.0: of_irq_parse_pci() failed with rc=-22
  pci 0000:00:0c.0: BAR 0: assigned [mem 0x58000000-0x58007fff]
  pci 0000:00:09.2: BAR 0: assigned [mem 0x58008000-0x580080ff]
  pci 0000:00:09.0: BAR 4: assigned [io  0x1000-0x101f]
  pci 0000:00:09.1: BAR 4: assigned [io  0x1020-0x103f]
  pci 0000:00:09.0: enabling device (0140 -> 0141)
  pci 0000:00:09.0: HCRESET not completed yet!
  pci 0000:00:09.1: enabling device (0140 -> 0141)
  pci 0000:00:09.1: HCRESET not completed yet!
  pci 0000:00:09.2: enabling device (0140 -> 0142)
  rt61pci 0000:00:0c.0: enabling device (0140 -> 0142)
  ieee80211 phy0: rt2x00_set_chip: Info - Chipset detected -
     rt: 2561, rf: 0003, rev: 000c
  ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
  ehci-pci: EHCI PCI platform driver
  ehci-pci 0000:00:09.2: EHCI Host Controller
  ehci-pci 0000:00:09.2: new USB bus registered, assigned bus number 1
  ehci-pci 0000:00:09.2: irq 125, io mem 0x58008000
  ehci-pci 0000:00:09.2: USB 2.0 started, EHCI 1.00
  hub 1-0:1.0: USB hub found
  hub 1-0:1.0: 4 ports detected
  uhci_hcd: USB Universal Host Controller Interface driver
  uhci_hcd 0000:00:09.0: UHCI Host Controller
  uhci_hcd 0000:00:09.0: new USB bus registered, assigned bus number 2
  uhci_hcd 0000:00:09.0: HCRESET not completed yet!
  uhci_hcd 0000:00:09.0: irq 123, io base 0x00001000
  hub 2-0:1.0: USB hub found
  hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
  uhci_hcd 0000:00:09.1: UHCI Host Controller
  uhci_hcd 0000:00:09.1: new USB bus registered, assigned bus number 3
  uhci_hcd 0000:00:09.1: HCRESET not completed yet!
  uhci_hcd 0000:00:09.1: irq 124, io base 0x00001020
  hub 3-0:1.0: USB hub found
  hub 3-0:1.0: config failed, hub doesn't have any ports! (err -19)
  scsi 0:0:0:0: Direct-Access     USB      Flash Disk       1.00 PQ: 0 ANSI: 2
  sd 0:0:0:0: [sda] 7900336 512-byte logical blocks: (4.04 GB/3.77 GiB)
  sd 0:0:0:0: [sda] Write Protect is off
  sd 0:0:0:0: [sda] No Caching mode page found
  sd 0:0:0:0: [sda] Assuming drive cache: write through
   sda: sda1 sda2 sda3
  sd 0:0:0:0: [sda] Attached SCSI removable disk
  ieee80211 phy0: rt2x00lib_request_firmware: Info -
     Loading firmware file 'rt2561s.bin'
  ieee80211 phy0: rt2x00lib_request_firmware: Info -
     Firmware detected - version: 0.8
  IPv6: ADDRCONF(NETDEV_UP): wlan0: link is not ready

  $ lspci
  00:00.0 Class 0600: 159b:4321
  00:09.2 Class 0c03: 1106:3104
  00:09.0 Class 0c03: 1106:3038
  00:09.1 Class 0c03: 1106:3038
  00:0c.0 Class 0280: 1814:0301

  $ cat /proc/interrupts
	     CPU0
  123:          0       PCI   0 Edge      uhci_hcd:usb2
  124:          0       PCI   1 Edge      uhci_hcd:usb3
  125:        159       PCI   2 Edge      ehci_hcd:usb1
  126:       1082       PCI   3 Edge      rt61pci

  $ cat /proc/iomem
  50000000-500000ff : /soc/pci@50000000
  58000000-5fffffff : Gemini PCI MEM
    58000000-58007fff : 0000:00:0c.0
      58000000-58007fff : 0000:00:0c.0
    58008000-580080ff : 0000:00:09.2
      58008000-580080ff : ehci_hcd

The EHCI USB hub works fine; I can mount and manage files and the IRQs just
keep ticking up.  I can issue iwlist wlan0 scanning and see all the WLANs
here.  I don't have wpa_supplicant so have not tried connecting to them.

[bhelgaas: fold in %pap change from Arnd Bergmann <arnd@arndb.de>]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
CC: Janos Laube <janos.dev@gmail.com>
CC: Paulius Zaleckas <paulius.zaleckas@gmail.com>
CC: Hans Ulli Kroll <ulli.kroll@googlemail.com>
CC: Florian Fainelli <f.fainelli@gmail.com>
CC: Feng-Hsin Chiang <john453@faraday-tech.com>
CC: Greentime Hu <green.hu@gmail.com>

Group all the PCI drivers that use DesignWare core in dwc directory.
dwc IP is capable of operating in both host mode and device mode and
keeping it inside the *host* directory is misleading.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jingoohan1@gmail.com>
Acked-By: NJoao Pinto <jpinto@synopsys.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Minghuan Lian <minghuan.Lian@freescale.com>
Cc: Mingkai Hu <mingkai.hu@freescale.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Cc: Niklas Cassel <niklas.cassel@axis.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Zhou Wang <wangzhou1@hisilicon.com>
Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Cc: Stanimir Varbanov <svarbanov@mm-sol.com>

Add Makefile comments to explain the Kconfig and build strategy for ARM64
drivers that work around not-quite-ECAM issues.  No functional change
intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

PCIe controllers in X-Gene SoCs are not ECAM compliant: software needs to
configure additional controller's register to address device at
bus:dev:function.

Add a quirk to discover controller MMIO register space and configure
controller registers to select and address the target secondary device.

The quirk will only be applied for X-Gene PCIe MCFG table with
OEM revison 1, 2, 3 or 4 (PCIe controller v1 and v2 on X-Gene SoCs).
Tested-by: NJon Masters <jcm@redhat.com>
Signed-off-by: NDuc Dang <dhdang@apm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

ThunderX pass1.x requires to emulate the EA headers for on-chip devices
hence it has to use custom pci_thunder_ecam_ops for accessing PCI config
space (pci-thunder-ecam.c). Add new entries to MCFG quirk array where it
can be applied while probing ACPI based PCI host controller.

ThunderX pass1.x is using the same way for accessing off-chip devices
(so-called PEM) as silicon pass-2.x so we need to add PEM quirk entries
too.

Quirk is considered for ThunderX silicon pass1.x only which is identified
via MCFG revision 2.

ThunderX pass 1.x requires the following accessors:

  NUMA node 0 PCI segments  0- 3: pci_thunder_ecam_ops (MCFG quirk)
  NUMA node 0 PCI segments  4- 9: thunder_pem_ecam_ops (MCFG quirk)
  NUMA node 1 PCI segments 10-13: pci_thunder_ecam_ops (MCFG quirk)
  NUMA node 1 PCI segments 14-19: thunder_pem_ecam_ops (MCFG quirk)

[bhelgaas: change Makefile/ifdefs so quirk doesn't depend on
CONFIG_PCI_HOST_THUNDER_ECAM]
Signed-off-by: NTomasz Nowicki <tn@semihalf.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

ThunderX PCIe controller to off-chip devices (so-called PEM) is not fully
compliant with ECAM standard. It uses non-standard configuration space
accessors (see thunder_pem_ecam_ops) and custom configuration space
granulation (see bus_shift = 24). In order to access configuration space
and probe PEM as ACPI-based PCI host controller we need to add MCFG quirk
infrastructure. This involves:
1. A new thunder_pem_acpi_init() init function to locate PEM-specific
   register ranges using ACPI.
2. Export PEM thunder_pem_ecam_ops structure so it is visible to MCFG quirk
   code.
3. New quirk entries for each PEM segment. Each contains platform IDs,
   mentioned thunder_pem_ecam_ops and CFG resources.

Quirk is considered for ThunderX silicon pass2.x only which is identified
via MCFG revision 1.

ThunderX pass 2.x requires the following accessors:

  NUMA Node 0 PCI segments  0- 3: pci_generic_ecam_ops (ECAM-compliant)
  NUMA Node 0 PCI segments  4- 9: thunder_pem_ecam_ops (MCFG quirk)
  NUMA Node 1 PCI segments 10-13: pci_generic_ecam_ops (ECAM-compliant)
  NUMA Node 1 PCI segments 14-19: thunder_pem_ecam_ops (MCFG quirk)

[bhelgaas: adapt to use acpi_get_rc_resources(), update Makefile/ifdefs so
quirk doesn't depend on CONFIG_PCI_HOST_THUNDER_PEM]
Signed-off-by: NTomasz Nowicki <tn@semihalf.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

The PCIe controller in Hip05/Hip06/Hip07 SoCs is not completely
ECAM-compliant.  It is non-ECAM only for the RC bus config space; for any
other bus underneath the root bus it does support ECAM access.

Add specific quirks for PCI config space accessors.  This involves:
1. New initialization call hisi_pcie_init() to obtain RC base
addresses from PNP0C02 at the root of the ACPI namespace (under \_SB).
2. New entry in common quirk array.

[bhelgaas: move to pcie-hisi.c and change Makefile/ifdefs so quirk doesn't
depend on CONFIG_PCI_HISI]
Signed-off-by: NDongdong Liu <liudongdong3@huawei.com>
Signed-off-by: NGabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Move the driver source and Kconfig to the PCI host bridge drivers directory
and move the config option to a more appropriate sub-menu instead of
occupying the top-level location.

Update the Kconfig option with the X86_64 dependency that was implicitly
included from the previous location, and add information about the module
name when built as a loadable module.
Signed-off-by: NKeith Busch <keith.busch@intel.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
CC: Jon Derrick <jonathan.derrick@intel.com>

Add support for the Rockchip PCIe controller found on RK3399 SoC platform.

[bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other
fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me,
uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>]
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NBrian Norris <briannorris@chromium.org>

Add a driver for the Aardvark PCIe controller used on the Marvell Armada
3700 ARM64 SoC.

Based on work done by Hezi Shahmoon <hezi.shahmoon@marvell.com> and Marcin
Wojtas <mw@semihalf.com>.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

The Axis ARTPEC-6 SoC integrates a PCIe controller from Synopsys.  Add a
new driver that provides the small glue needed to use the existing
DesignWare driver to make it work on the Axis ARTPEC-6 SoC.

[bhelgaas: return errors directly without gotos, fold in section mismatch
fix]
Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

The Marvell Armada 7K/8K SoCs integrate a PCIe controller from Synopsys.
Add a new driver that provides the small glue needed to use the existing
Designware driver to make it work on Marvell Armada 7K/8K SoCs.

The MSI support will be enabled at a later point.

[bhelgaas: use dev_dbg(), dw_pcie_wait_for_link()]
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

It appears that Gen2 is a misnomer for the R-Car PCIE driver
which also supports Gen 1 and Gen 3 SoCs. Accordingly, drop Gen 2
from the help text and Kconfig symbol.

Also, re-arange the Kconfig symbol name to use PCIE as the prefix.
This appears to be in keeping with other PCIE Kconfig symbols.
Reported-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add a reference platform driver for PCI RC IP Protoyping Kits based on the
ARC SDP.

[bhelgaas: changelog, split patch up, MAINTAINERS update]
Signed-off-by: NJoao Pinto <jpinto@synopsys.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NPratyush Anand <pratyush.anand@gmail.com>

The cavium,pci-thunder-ecam devices are exactly ECAM-based PCI root
complexes.  These root complexes (loosely referred to as ECAM units in the
hardware manuals) are used to access the Thunder on-chip devices.  They
are special in that all the BARs on devices behind these root complexes are
at fixed addresses.

Add a driver for these devices that synthesizes Enhanced Allocation (EA)
capability entries for each BAR.

Since this EA synthesis is needed for exactly two chip models, we can hard-
code some assumptions about the device topology and the layout of the
config space of specific DEVFNs in the driver.

[bhelgaas: changelog, whitespace]
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NRob Herring <robh@kernel.org>

The root complexes used to access off-chip PCIe devices (called PEM units
in the hardware manuals) on some Cavium ThunderX processors require quirky
access methods for the config space of the PCIe bridge.

Add a driver to provide these config space accessor functions.  Use the
pci-host-common code to configure the PCI machinery.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Move pci_host_common_probe() and associated functions to pci-host-common.c,
where it can be shared with other drivers.  Make it public (not static)
and update Kconfig and Makefile to build it.  No functional change
intended.

[bhelgaas: split into separate patch, changelog]
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NWill Deacon <will.deacon@arm.com>

Add PCIe Root Port driver for Xilinx PCIe NWL bridge IP.

[bhelgaas: wait for link like dw_pcie_wait_for_link(), simplify bitmap
error path, typos, whitespace, fold in Dan Carpenter's PTR_ERR() fix]
Signed-off-by: NBharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: NRavi Kiran Gummaluri <rgummal@xilinx.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NRob Herring <robh@kernel.org>

Add a new driver which exposes a root PCI bus whenever a PCI Express device
is passed through to a guest VM under Hyper-V.  The device can be single-
or multi-function.  The interrupts for the devices are managed by an IRQ
domain, implemented within the driver.

[bhelgaas: fold in race condition fix (http://lkml.kernel.org/r/1456340196-13717-1-git-send-email-jakeo@microsoft.com)]
Signed-off-by: NJake Oshins <jakeo@microsoft.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add PCIe MSI support for both PAXB and PAXC interfaces on all iProc-based
platforms.

The iProc PCIe MSI support deploys an event queue-based implementation.
Each event queue is serviced by a GIC interrupt and can support up to 64
MSI vectors.  Host memory is allocated for the event queues, and each event
queue consists of 64 word-sized entries.  MSI data is written to the lower
16-bit of each entry, whereas the upper 16-bit of the entry is reserved for
the controller for internal processing.

Each event queue is tracked by a head pointer and tail pointer.  Head
pointer indicates the next entry in the event queue to be processed by
the driver and is updated by the driver after processing is done.
The controller uses the tail pointer as the next MSI data insertion
point.  The controller ensures MSI data is flushed to host memory before
updating the tail pointer and then triggering the interrupt.

MSI IRQ affinity is supported by evenly distributing the interrupts to each
CPU core.  MSI vector is moved from one GIC interrupt to another in order
to steer to the target CPU.

Therefore, the actual number of supported MSI vectors is:

  M * 64 / N

where M denotes the number of GIC interrupts (event queues), and N denotes
the number of CPU cores.

This iProc event queue-based MSI support should not be used with newer
platforms with integrated MSI support in the GIC (e.g., giv2m or
gicv3-its).

[bhelgaas: fold in Kconfig fixes from Arnd Bergmann <arnd@arndb.de>]
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NVikram Prakash <vikramp@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>

The PCIe driver reuses the Designware common code for host and MSI
initialization, and also programs the Qualcomm application specific
registers.

[bhelgaas: remove COMPILE_TEST Kconfig dependency]
Signed-off-by: NStanimir Varbanov <svarbanov@mm-sol.com>
Signed-off-by: NStanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Add Altera PCIe MSI driver.  This soft IP supports a configurable number of
vectors, which is a DTS parameter.

[bhelgaas: Kconfig depend on PCIE_ALTERA, typos, whitespace]
Signed-off-by: NLey Foon Tan <lftan@altera.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NRob Herring <robh@kernel.org>

Add PCIe host support for HiSilicon SoC Hip05, related DT binding
documentation, and maintainer update.

[bhelgaas: changelog, 32-bit only config write warning text]
Signed-off-by: NZhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: NGabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Nliudongdong <liudongdong3@huawei.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org> (DT binding)

Add the Altera PCIe host controller driver.

[bhelgaas: whitespace, fold in DT and maintainer updates, OF_PCI
dependency from Arnd]
Signed-off-by: NLey Foon Tan <lftan@altera.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: Rob Herring <robh@kernel.org> (DT binding)

APM X-Gene v1 SoC supports its own implementation of MSI, which is not
compliant to GIC V2M specification for MSI Termination.

There is a single MSI block in X-Gene v1 SOC which serves all 5 PCIe ports.
This MSI block supports 2048 MSI termination ports coalesced into 16
physical HW IRQ lines and shared across all 5 PCIe ports.

As there are only 16 HW IRQs to serve 2048 MSI vectors, to support
set_affinity correctly for each MSI vectors, the 16 HW IRQs are statically
allocated to 8 X-Gene v1 cores (2 HW IRQs for each cores).  To steer MSI
interrupt to target CPU, MSI vector is moved around these HW IRQs lines.
With this approach, the total MSI vectors this driver supports is reduced
to 256.

[bhelgaas: squash doc, driver, maintainer update]
Signed-off-by: NDuc Dang <dhdang@apm.com>
Signed-off-by: NTanmay Inamdar <tinamdar@apm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>

This driver adds support for the PCIe 2.0 controller found on the BCMA bus.
This controller can be found on (mostly) all Broadcom BCM470X / BCM5301X
ARM SoCs.

The driver found in the Broadcom SDK does some more stuff, like setting up
some DMA memory areas, chaining MPS and MRRS to 512 and also some PHY
changes like "improving" the PCIe jitter and doing some special
initialization for the 3rd PCIe port.

This was tested on a bcm4708 board with 2 PCIe ports and wireless cards
connected to them.

PCI_DOMAINS is needed by this driver, because normally there is more than
one PCIe controller and without PCI_DOMAINS only the first controller gets
registered.  This controller gets 6 IRQs; the last one is trigged by all
IRQ events.

[bhelgaas: fix "GPLv2" MODULE_LICENSE typo]
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NRafał Miłecki <zajec5@gmail.com>
Acked-by: NRay Jui <rjui@broadcom.com.com>

Add support for the Broadcom iProc PCIe controller.

pcie-iproc.c is the common core driver, and a front-end bus interface needs
to be added to support different bus interfaces.

pcie-iproc-platform.c contains the support for the platform bus interface.
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

This converts the Versatile PCI host code to a platform driver using the
commom DT parsing and setup.  The driver uses only an empty ARM
pci_sys_data struct and does not use pci_common_init_dev init function.
The old host code will be removed in a subsequent commit when Versatile is
completely converted to DT.

I've tested this on QEMU with the sym53c8xx driver in both i/o and memory
mapped modes.
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
CC: Russell King <linux@arm.linux.org.uk>
CC: Peter Maydell <peter.maydell@linaro.org>

Add support for Freescale Layerscape PCIe controller.  This driver re-uses
the Synopsis DesignWare core code.

[bhelgaas: add Kconfig dependency on CONFIG_ARM]
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Add the AppliedMicro X-Gene SOC PCIe host controller driver.  The X-Gene
PCIe controller supports up to 8 lanes and GEN3 speed.  The X-Gene SOC
supports up to 5 PCIe ports.

[bhelgaas: folded in MAINTAINERS and bindings updates]
Tested-by: NMing Lei <ming.lei@canonical.com>
Tested-by: NDann Frazier <dann.frazier@canonical.com>
Signed-off-by: NTanmay Inamdar <tinamdar@apm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Liviu Dudau <Liviu.Dudau@arm.com> (driver)

The Keystone PCIe controller is based on v3.65 version of the Designware
h/w.  Main differences are:

    1. No ATU support
    2. Legacy and MSI IRQ functions are implemented in application register
       space
    3. MSI interrupts are multiplexed over 8 IRQ lines to the Host side.

All of the application register space handing code is organized into
pci-keystone-dw.c and the functions are called from pci-keystone.c to
implement PCI controller driver.  Also add necessary DT documentation and
update the MAINTAINERS file for the driver.

[bhelgaas: spelling and whitespace fixes]
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Mohit Kumar <mohit.kumar@st.com>
CC: Pratyush Anand <pratyush.anand@st.com>
CC: Jingoo Han <jg1.han@samsung.com>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>

This is the driver for Xilinx AXI PCIe Host Bridge Soft IP.

[bhelgaas: minor whitespace fixes]
Signed-off-by: NSrikanth Thokala <sthokal@xilinx.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Add support for PCIe controller in DRA7xx.  This driver re-uses the
designware core code that is already present in kernel.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>

ARM based ST Microelectronics's SPEAr1310 and SPEAr1340 SOCs have onchip
designware PCIe controller. To make that usable, this patch adds a wrapper
driver based on existing designware driver.

Adds bindings for this new driver and update MAINTAINERS as well.

Cc: linux-pci@vger.kernel.org
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NPratyush Anand <pratyush.anand@st.com>
Signed-off-by: NMohit Kumar <mohit.kumar@st.com>
[viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>

Add support for a generic PCI host controller, such as a
firmware-initialised device with static windows or an emulation by
something such as kvmtool.

The controller itself has no configuration registers and has its address
spaces described entirely by the device-tree (using the bindings from
ePAPR).  Both CAM and ECAM are supported for Config Space accesses.

Add corresponding documentation for the DT binding.

[bhelgaas: currently uses the ARM-specific pci_common_init_dev() interface]
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NLiviu Dudau <liviu.dudau@arm.com>

This PCIe Host driver currently does not support MSI, so cards fall back to
INTx interrupts.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>

This adds internal PCI controller driver for R-Car Gen2 SoC.  There are
three PCI controllers available with only a single EHCI/OHCI device
built-in on each PCI bus.  This gives us three USB channels.  Channel 0 is
shared with the USBHS device, while channel 2 is shared with the USBSS.

The PCI controllers do not support I/O port space mapping, and it is not
needed here.
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>