1. 04 7月, 2016 1 次提交
  2. 03 7月, 2016 1 次提交
  3. 02 7月, 2016 1 次提交
    • C
      drm/i915: Spin after waking up for an interrupt · f69a02c9
      Chris Wilson 提交于
      When waiting for an interrupt (waiting for the engine to complete some
      work), we know we are the only waiter to be woken on this engine. We also
      know when the GPU has nearly completed our request (or at least started
      processing it), so after being woken and we detect that the GPU is
      active and working on our request, allow us the bottom-half (the first
      waiter who wakes up to handle checking the seqno after the interrupt) to
      spin for a very short while to reduce client latencies.
      
      The impact is minimal, there was an improvement to the realtime-vs-many
      clients case, but exporting the function proves useful later. However,
      it is tempting to adjust irq_seqno_barrier to include the spin. The
      problem is first ensuring that the "start-of-request" seqno is coherent
      as we use that as our basis for judging when it is ok to spin. If we
      could, spinning there could dramatically shorten some sleeps, and allow
      us to make the barriers more conservative to handle missed seqno writes
      on more platforms (all gen7+ are known to have the occasional issue, at
      least).
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-7-git-send-email-chris@chris-wilson.co.uk
      f69a02c9
  4. 30 6月, 2016 17 次提交
  5. 29 6月, 2016 2 次提交
  6. 24 6月, 2016 4 次提交
  7. 22 6月, 2016 1 次提交
    • I
      drm/i915/ibx, cpt: Don't attempt to register eDP if LVDS was detected · 97a824e1
      Imre Deak 提交于
      Atm on IBX/CPT we attempt to detect if eDP is present even if LVDS was
      already detected and an encoder for it was registered. This involves
      trying to read out the eDP DPCD, which in turn needs the same power
      sequencer that LVDS uses. Poking at the VDD line at an unexpected time
      may or may not interfere with the LVDS panel, but it's probably safer to
      prevent this. Registering both an LVDS and an eDP connector would also
      present a similar problem accessing the shared PPS at any point later in
      an unexpected way.
      
      We also need this to be able fix PPS initialization before its first use
      in the next patch. For that we want to be sure that PPS is not in use
      by LVDS.
      
      v2:
      - Split out the PPS init fix to a separate patch. (Chris)
      - Add comment about eDP init depending on LVDS init. (Chris)
      - Make the use of the intel_encoder ptr less error prone.
      v3:
      - Use IBX/CPT reference instead of the incorrect ILK, add a WARN about
        this. (Ville)
      v4:
      - Use a helper to get the lvds encoder instead of opencoding the same.
        (Ville)
      
      CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
      CC: Chris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NImre Deak <imre.deak@intel.com>
      Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v2)
      Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v3)
      Link: http://patchwork.freedesktop.org/patch/msgid/1466499109-20240-2-git-send-email-imre.deak@intel.com
      97a824e1
  8. 19 6月, 2016 2 次提交
  9. 17 6月, 2016 2 次提交
  10. 16 6月, 2016 6 次提交
  11. 15 6月, 2016 1 次提交
    • L
      drm/i915/ilk: Don't disable SSC source if it's in use · 1c1a24d2
      Lyude 提交于
      Thanks to Ville Syrjälä for pointing me towards the cause of this issue.
      
      Unfortunately one of the sideaffects of having the refclk for a DPLL set
      to SSC is that as long as it's set to SSC, the GPU will prevent us from
      powering down any of the pipes or transcoders using it. A couple of
      BIOSes enable SSC in both PCH_DREF_CONTROL and in the DPLL
      configurations. This causes issues on the first modeset, since we don't
      expect SSC to be left on and as a result, can't successfully power down
      the pipes or the transcoders using it. Here's an example from this Dell
      OptiPlex 990:
      
      [drm:intel_modeset_init] SSC enabled by BIOS, overriding VBT which says disabled
      [drm:intel_modeset_init] 2 display pipes available.
      [drm:intel_update_cdclk] Current CD clock rate: 400000 kHz
      [drm:intel_update_max_cdclk] Max CD clock rate: 400000 kHz
      [drm:intel_update_max_cdclk] Max dotclock rate: 360000 kHz
      vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
      [drm:intel_crt_reset] crt adpa set to 0xf40000
      [drm:intel_dp_init_connector] Adding DP connector on port C
      [drm:intel_dp_aux_init] registering DPDDC-C bus for card0-DP-1
      [drm:ironlake_init_pch_refclk] has_panel 0 has_lvds 0 has_ck505 0
      [drm:ironlake_init_pch_refclk] Disabling SSC entirely
      … later we try committing the first modeset …
      [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff88041b02e800 for pipe A
      [drm:intel_dump_pipe_config] cpu_transcoder: A
      …
      [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xc4016001, dpll_md: 0x0, fp0: 0x20e08, fp1: 0x30d07
      [drm:intel_dump_pipe_config] planes on this crtc
      [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 enabled
      [drm:intel_dump_pipe_config]     FB:42, fb = 800x600 format = 0x34325258
      [drm:intel_dump_pipe_config]     scaler:0 src (0, 0) 800x600 dst (0, 0) 800x600
      [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0
      [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0
      [drm:intel_get_shared_dpll] CRTC:26 allocated PCH DPLL A
      [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
      [drm:ilk_audio_codec_disable] Disable audio codec on port C, pipe A
      [drm:intel_disable_pipe] disabling pipe A
      ------------[ cut here ]------------
      WARNING: CPU: 1 PID: 130 at drivers/gpu/drm/i915/intel_display.c:1146 intel_disable_pipe+0x297/0x2d0 [i915]
      pipe_off wait timed out
      …
      ---[ end trace 94fc8aa03ae139e8 ]---
      [drm:intel_dp_link_down]
      [drm:ironlake_crtc_disable [i915]] *ERROR* failed to disable transcoder A
      
      Later modesets succeed since they reset the DPLL's configuration anyway,
      but this is enough to get stuck with a big fat warning in dmesg.
      
      A better solution would be to add refcounts for the SSC source, but for
      now leaving the source clock on should suffice.
      
      Changes since v4:
       - Fix calculation of final for systems with LVDS panels (fixes BUG() on
         CI test suite)
      Changes since v3:
       - Move temp variable into loop
       - Move checks for using_ssc_source to after we've figured out has_ck505
       - Add using_ssc_source to debug output
      Changes since v2:
       - Fix debug output for when we disable the CPU source
      Changes since v1:
       - Leave the SSC source clock on instead of just shutting it off on all
         of the DPLL configurations.
      
      Cc: stable@vger.kernel.org
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NLyude <cpaul@redhat.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Link: http://patchwork.freedesktop.org/patch/msgid/1465916649-10228-1-git-send-email-cpaul@redhat.com
      1c1a24d2
  12. 13 6月, 2016 2 次提交