- 07 6月, 2014 1 次提交
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由 Loc Ho 提交于
This patch adds APM X-Gene SoC RTC DTS entry Signed-off-by: NRameshwar Prasad Sahu <rsahu@apm.com> Signed-off-by: NLoc Ho <lho@apm.com> Cc: Jon Masters <jcm@redhat.com> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 04 5月, 2014 1 次提交
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由 Catalin Marinas 提交于
Since the default DMA ops for arm64 are non-coherent, mark the X-Gene controller explicitly as dma-coherent to avoid additional cache maintenance. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Cc: Loc Ho <lho@apm.com>
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- 18 3月, 2014 2 次提交
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由 Loc Ho 提交于
This patch adds APM X-Gene SoC AHCI SATA host controller DTS entries. Signed-off-by: NLoc Ho <lho@apm.com> Signed-off-by: NTuan Phan <tphan@apm.com> Signed-off-by: NSuman Tripathi <stripathi@apm.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NTejun Heo <tj@kernel.org>
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由 Loc Ho 提交于
This patch adds the DTS entries for the APM X-Gene SoC 15Gbps Multi-purpose PHY driver. The PHY for SATA controller 2 and 3 are enabled by default. Signed-off-by: NLoc Ho <lho@apm.com> Signed-off-by: NTuan Phan <tphan@apm.com> Signed-off-by: NSuman Tripathi <stripathi@apm.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NTejun Heo <tj@kernel.org>
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- 08 10月, 2013 1 次提交
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由 Loc Ho 提交于
clk: arm64: Add DTS clock entry for APM X-Gene Storm SoC with reference to reference, PCP PLL, SoC PLL, and Ethernet clocks. Signed-off-by: NLoc Ho <lho@apm.com> Signed-off-by: NKumar Sankaran <ksankaran@apm.com> Signed-off-by: NVinayak Kale <vkale@apm.com> Signed-off-by: NFeng Kan <fkan@apm.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 21 6月, 2013 1 次提交
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由 Vinayak Kale 提交于
This patch adds initial DTS files required for APM Mustang board. Signed-off-by: NKumar Sankaran <ksankaran@apm.com> Signed-off-by: NLoc Ho <lho@apm.com> Signed-off-by: NFeng Kan <fkan@apm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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