1. 05 7月, 2014 1 次提交
    • A
      spi/rockchip: add driver for Rockchip RK3xxx SoCs integrated SPI · 64e36824
      addy ke 提交于
      In order to facilitate understanding, rockchip SPI controller IP design
      looks similar in its registers to designware. But IC implementation
      is different from designware, So we need a dedicated driver for Rockchip
      RK3XXX SoCs integrated SPI. The main differences:
      
      - dma request line: rockchip SPI controller have two DMA request line
        for tx and rx.
      
      - Register offset:
                        RK3288        dw
        SPI_CTRLR0      0x0000        0x0000
        SPI_CTRLR1      0x0004        0x0004
        SPI_SSIENR      0x0008        0x0008
        SPI_MWCR        NONE          0x000c
        SPI_SER         0x000c        0x0010
        SPI_BAUDR       0x0010        0x0014
        SPI_TXFTLR      0x0014        0x0018
        SPI_RXFTLR      0x0018        0x001c
        SPI_TXFLR       0x001c        0x0020
        SPI_RXFLR       0x0020        0x0024
        SPI_SR          0x0024        0x0028
        SPI_IPR         0x0028        NONE
        SPI_IMR         0x002c        0x002c
        SPI_ISR         0x0030        0x0030
        SPI_RISR        0x0034        0x0034
        SPI_TXOICR      NONE          0x0038
        SPI_RXOICR      NONE          0x003c
        SPI_RXUICR      NONE          0x0040
        SPI_MSTICR      NONE          0x0044
        SPI_ICR         0x0038        0x0048
        SPI_DMACR       0x003c        0x004c
        SPI_DMATDLR     0x0040        0x0050
        SPI_DMARDLR     0x0044        0x0054
        SPI_TXDR        0x0400        NONE
        SPI_RXDR        0x0800        NONE
        SPI_IDR         NONE          0x0058
        SPI_VERSION     NONE          0x005c
        SPI_DR          NONE          0x0060
      
      - register configuration:
        such as SPI_CTRLRO in rockchip SPI controller:
          cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
              | (CR0_SSD_ONE << CR0_SSD_OFFSET);
          cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
          cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
          cr0 |= (rs->tmode << CR0_XFM_OFFSET);
          cr0 |= (rs->type << CR0_FRF_OFFSET);
        For more information, see RK3288 chip manual.
      
      - Wait for idle: Must ensure that the FIFO data has been sent out
        before the next transfer.
      Signed-off-by: Naddy ke <addy.ke@rock-chips.com>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      64e36824
  2. 15 6月, 2014 1 次提交
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  5. 12 6月, 2014 22 次提交