This is in preparation for clock providers to not have to deal with struct clk.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Instead of struct clk, as this should be only used by providers.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

As it's only used internally, in drivers/clk/clk.c.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

As __clk_release could call kfree on clk and then we wouldn't have a safe way
of getting the module that owns the clock.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Fixes: fcb0ee6a ("clk: Implement clk_unregister")
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

This patch adds the 2 physical clocks for the mmc (drive and sample). They're
mostly there for the phase properties, but they also show the true clock
(by dividing by RK3288_MMC_CLKGEN_DIV).

The drive and sample phases are generated by dividing an upstream parent clock
by 2, this allows us to adjust the phase by 90 deg.

There's also an option to have up to 255 delay elements (40-80 picoseconds long).
This driver uses those elements (under the assumption that they're 60 ps long)
to generate approximate 22.5 degrees options. 67.5 (22.5*3) might be as high as
90 deg if the delay elements are as big as 80 ps, so a finer division (smaller
than 22.5) was not picked because the phase might not be monotonic anymore.
Suggested-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NAlexandru M Stan <amstan@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This exposes the clock that comes out of the i2s block which generally
goes to the audio codec.
Signed-off-by: NSonny Rao <sonnyrao@chromium.org>
[removed CLK_SET_RATE_PARENT from original patch]
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The DMC clocks need to be turned off at runtime.  Use the newly
assigned clock IDs to export them.
Signed-off-by: NJeff Chen <cym@rock-chips.com>
[dianders: split into two patches; adjusted commit msg]
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

drivers/clk/clk-s2mps11.c:181:2-3: Unneeded semicolon

 Removes unneeded semicolon.

Generated by: scripts/coccinelle/misc/semicolon.cocci

CC: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: NFengguang Wu <fengguang.wu@intel.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

This patch adds the support for S2MPS13 PMIC clock which is same with existing
S2MPS14 RTC IP. But, S2MPS13 uses all of clocks (32khz_{ap|bt|cp}).
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Add the new flag to gpll and cpll on rk3188 and similar and to
gpll, cpll and npll on rk3288.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NKever Yang <kever.yang@rock-chips.com>

In some cases firmware brings up plls with different parameters than the ones
noted in the rate table for the specific frequency. These firmware-selected
parameters are worse than the tested ones in the pll rate tables but cannot
be changed by a simple clk_set_rate call when the rate stays the same.

Therefore add a ROCKCHIP_PLL_SYNC_RATE flag and implement an init callback
that checks the runtime-parameters against the matching rate table entry
and adjusts them to the table-ones if necessary.

If no rate table is set or the current rate does not match any rate-table
entry no changes are made.

Being able to limit this adjustment to specific plls is necessary to not
touch the ones supplying core components like the apll and dpll supplying
the armcores and dram.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NKever Yang <kever.yang@rock-chips.com>

In some cases we might need to access the data of the pll mux before the actual
mux gets registered - like in the following patch adding an init-callback.

Therefore populate pll_mux before registering the core pll-clock.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NKever Yang <kever.yang@rock-chips.com>

This adds a flag parameter to plls that allows us to create
special flags to tweak the behaviour of the plls if necessary.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NKever Yang <kever.yang@rock-chips.com>

A CLK_MUX_INDEX_BIT mux has one bit per parent, but the sun7i-a20-gmac-clk
has 2 bits selecting between 3 possible parents using values of 0, 1, 2,
which makes it a regular mux which should not have CLK_MUX_INDEX_BIT set in
its flag.

However we do not support parent 1 (an external clock), so use a table to
select parent 0 or 2, which are the 2 parents we support.

Note this has not been causing any issues sofar, because we start with a
parent setting of parent 0, and only ever re-parent to parent 2 (for which
we use an index of 1 as we skip parent 1) and with CLK_MUX_INDEX_BIT set
we write a value of 2 for index 1.

Tested on both a cubietruck (which uses rgmii mode) as well as a cs908
(an a31s board which uses mii mode).
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Some clock modules on the A31 use PLL6x2 as one of their inputs.
This patch changes the PLL6 implementation for A31 to a divs clock,
i.e. clock with multiple outputs that have different dividers.
The first output will be the normal PLL6 output, and the second
will be PLL6x2.

This patch fixes the PLL6 N factor in the clock driver, and removes
any /2 dividers in the PLL6 factors clock part. The N factor counts
from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Currently sunxi_divs_clk_setup assumes the number of child clocks
to be the same as the number of clock-output-names, and a maximum
of SUNXI_DIVS_MAX_QTY child clocks.

On sun6i, PLL6 only has 1 child clock, but the parent would be used
as well, thereby also having it's own clock-output-names entry. This
results in an extra bogus clock being registered.

This patch adds an entry for the number of child clocks alongside
the data structures for them.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This driver does not match the hardware, which is actually compatible
to sun4i-a10-apb1-clk. Since we've switch to the correct one, drop
this driver.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The USB HSIC PHY clock divider is set in the register RK2928_CLKSEL_CON(11).
Signed-off-by: NJulien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

In rk3188 clock branches, spdif_pre gate was set to RK2928_CLKGATE_CON(13) bit 13.
This appears to be a copy-paste error because such a register does not exist.
We correct it to RK2928_CLKGATE_CON(0) and find out that the rk3188 spdif clock
is the same as the rk3066 spdif clock, so we move it to the common clock branches.
Signed-off-by: NJulien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Use __initconst instead of __initdata for constant init data.
Signed-off-by: NBintian Wang <bintian.wang@huawei.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

If CLK_MUX_INDEX_BIT is set, then each bit turns on / off a single parent,
so theoretically multiple parents could be enabled at the same time, but in
practice only one bit should ever be 1. So to select parent 0, set
the register (*) to 0x01, to select parent 1 set it 0x02, parent 2, 0x04,
parent 3, 0x08, etc.

But the current code does:

                if (mux->flags & CLK_MUX_INDEX_BIT)
                        index = (1 << ffs(index));

Which means that:

For an input index of 0, ffs returns 0, so we set the register
to 0x01, ok.

For an input index of 1, ffs returns 1, so we set the register
to 0x02, ok.

For an input index of 2, ffs returns 2, so we set the register
to 0x04, ok.

For an input index of 3, ffs returns 1, so we set the register
to 0x02, not good!

The code should simply be:

                if (mux->flags & CLK_MUX_INDEX_BIT)
                        index = 1 << index;

Which always does the right thing, this commit fixes this.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

It's the same to the next statement, "ret = clk->parent". I think compiler will
optimize it, it's just not looking well.
Signed-off-by: NZhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

The parent clock for hclk_lcdc1 was set to aclk_cpu instead of hclk_cpu.
Signed-off-by: NJulien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Have each pxa variant (pxa25x, pxa27x, pxa3xx) have its own device-tree
clock initializing function, to be able to register its own specific
core clocks.

Apply that change specifically to pxa27x.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

As the clock descriptions are constant and only usefull at init time,
mark them as such by :
 - spliting clock description (desc) and clock private data (dynamic)
 - mark __initdata clock descriptions

This makes all the register and descriptions of the clocks to go after
kernel init phase.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Trivial fix to check the A bit of CCCR for memory frequency
calculations, where the shift of the bit index was missing, triggering a
wrong calculation of memory frequency.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Move pxa25x clock drivers from arch/arm/mach-pxa to driver/clk.
In the move :
 - convert to new clock framework legacy clocks
 - provide clocks as before for platform data based boards
 - provide clocks through devicetree with clk-pxa-dt

This is the preliminary step in the conversion. The remaining steps are
:
 - pxa3xx
 - once PXA is fully converted to device tree, if that happens,
   clk-pxa2* and clk-pxa3* should only hold the core clocks which cannot
   be described in devicetree.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Tested-by: NDmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Commit 79c6ab50 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in
v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the
recalc_rate() and round_rate() clock callbacks to be omitted.

However using this flag has the unfortunate side effect of causing the
clock recalculation code when a clock rate change is attempted to always
treat it as a pass-through clock, i.e. with a fixed divide of 1, which
may not be the case. Child clock rates are then recalculated using the
wrong parent rate.

Therefore instead of dropping the recalc_rate() and round_rate()
callbacks, alter clk_divider_bestdiv() to always report the current
divider as the best divider so that it is never altered.

For me the read only clock was the system clock, which divided the PLL
rate by 2, from which both the UART and the SPI clocks were divided.
Initial setting of the UART rate set it correctly, but when the SPI
clock was set, the other child clocks were miscalculated. The UART clock
was recalculated using the PLL rate as the parent rate, resulting in a
UART new_rate of double what it should be, and a UART which spewed forth
garbage when the rate changes were propagated.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: Max Schwarz <max.schwarz@online.de>
Cc: <stable@vger.kernel.org> # v3.16+
Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

There is a duplication in a clock name for apq8084 platform that causes
the following warning: "RBCPR_CLK_SRC" redefined

Resolve this by adding a MMSS_ prefix to this clock and making its name
coherent with msm8974 platform.

Fixes: 2b46cd23 ("clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) support")
Signed-off-by: NGeorgi Djakov <gdjakov@mm-sol.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

First check for rate == 0 in set_rate and round_rate to avoid div by zero.
Then, in order to get the closest rate, round all divisions to the closest
result instead of rounding them down.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

at91rm9200_clk_usb_set_rate might fail depending on the requested rate,
because the parent_rate / rate remainder is not necessarily zero.
Moreover, when rounding down the calculated rate we might alter the
divisor calculation and end up with an invalid divisor.

To solve those problems, accept a non zero remainder, and always round
division to the closest result.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: NAndreas Henriksson <andreas.henriksson@endian.se>
Tested-by: NAndreas Henriksson <andreas.henriksson@endian.se>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

According to rk3288 trm, the mux selector locate at bit[12:11]
of CRU_CLKSEL13_CON shows:
2'b00: select HOST0 USB pll clock (clk_otgphy1)
2'b01: select HOST1 USB pll clock (clk_otgphy2)
2'b10: select OTG USB pll clock   (clk_otgphy0)

The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3
- clk_otgphy0 -> USB PHY OTG
- clk_otgphy1 -> USB PHY host0
- clk_otgphy2 -> USB PHY host1
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

According to rk3288 trm, the clk_usbphy480m_gate is located at
bit 14 of CRU_CLKGATE5_CON register.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Currently there is no driver owning these clocks and they have to stay
up for the system to function properly, so let's mark them as
CLK_IGNORE_UNUSED.

Without this patch we have trouble with suspend/resume and we have
trouble turning the eDP back on if it ever idles off.
Signed-off-by: NDmitry Torokhov <dtor@chromium.org>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

It adds the DT support for mmp2 clock subsystem.
Signed-off-by: NChao Xie <chao.xie@marvell.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

It adds the DT support for pxa910 clock subsystem.
Signed-off-by: NChao Xie <chao.xie@marvell.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

It adds the DT support for pxa168 clock subsystem.
Signed-off-by: NChao Xie <chao.xie@marvell.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Some clock control regsiter has bit to reset the cotroller.
So before enable the clock, we need deassert the reset pin.
Make use of reset controller framework to export reset interface
for device drivers, then device driver can control the reset action.
Signed-off-by: NChao Xie <chao.xie@marvell.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

In order to support DT for mmp SOC clocks, it defines
some basic APIs which are shared by all mmp SOC clock
units.
Signed-off-by: NChao Xie <chao.xie@marvell.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>