Specifies the required clock inputs for each supported compatible.
Armada 370 requires a single clock phandle, and Armada XP requires
two clock phandles with clock-names "nbclk" and "fixed".

Cc: devicetree@vger.kernel.org
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

This commit fixes the DT binding for the Armada 370/XP SoC timer.
The previous "marvell,armada-370-xp-timer" compatible is removed and
two new compatible strings are introduced: "marvell,armada-xp-timer"
and "marvell,armada-370-timer".

The rationale behind this change is that the Armada 370 SoC and the
Armada XP SoC timers are not really compatible:

  * Armada 370 has no 25 MHz fixed timer.

  * Armada XP cannot work properly without such 25 MHz fixed timer
    as doing otherwise leads to using a clocksource whose frequency
    varies when doing cpufreq frequency changes.

This commit also removes the "marvell,timer-25Mhz" property, given
it's now meaningless.

Cc: devicetree@vger.kernel.org
Acked-by: NJason Cooper <jason@lakedaemon.net>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Add a binding for the arm architected timer hardware's memory
mapped interface. The mmio timer hardware is made up of one base
frame and a collection of up to 8 timer frames, where each of the
8 timer frames can have either one or two views. A frame
typically maps to a privilege level (user/kernel, hypervisor,
secure). The first view has full access to the registers within a
frame, while the second view can be restricted to particular
registers within a frame. Each frame must support a physical
timer. It's optional for a frame to support a virtual timer.

Cc: devicetree-discuss@lists.ozlabs.org
Cc: Marc Zyngier <Marc.Zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Rob Herring <robherring2@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NMark Rutland <mark.rutland@arm.com>

1. describe compatible variable "Must be" instead of "Should be".
2. change description so it's from the point of view of the device
Signed-off-by: NJonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Fix device tree bindings document with the correct clock name.
Signed-off-by: NJonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: NGrant Likely <grant.likely@linaro.org>

This prefix will be used in various compatible properties
for the devices from Qualcomm Atheros, Inc.

Cc: Luis R. Rodriguez <rodrigue@qca.qualcomm.com>
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Signed-off-by: NGrant Likely <grant.likely@linaro.org>

This patch adds an clocksource driver for the main timer(s)
found on MOXA ART SoCs.

The MOXA ART SoC provides three separate timers with individual
count/load/match registers, two are used here:

TIMER1: clockevents, used to support oneshot and periodic events
TIMER2: set up as a free running counter, used as clocksource

Timers are preconfigured by bootloader to count down and interrupt
on match or zero. Count increments every APB clock cycle and is
automatically reloaded when it reaches zero.
Signed-off-by: NJonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

commit 28d1e8cd
(regulator: palma: add ramp delay support through regulator constraints)

Removed the regulator's ti,step option from driver without updating the
documentation.

So, remove from documentation and example as well.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

commit 3c870e3f
(regulator: palmas: Change the DT node property names to follow the convention)

Missed updating mode-sleep from sleep-mode. Fix the same.

Documentation example seems proper for this property.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

spll_gate was added with commit b7eed207
"ARM: imx27: add a clock gate to activate SPLL clock".

spll_gate is missing in the devicetree clock documentation for imx27. This
patch adds it to the list of clocks in the documentation.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch adds the driver for the watchdog devices found on MEN Mikro
Elektronik A21 VMEbus CPU Carrier Boards. It has DT-support and uses the
watchdog framework.
Signed-off-by: NJohannes Thumshirn <johannes.thumshirn@men.de>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>

This adds a driver for watchdog timer hardware present on Broadcom BCM2835 SoC,
used in Raspberry Pi and Roku 2 devices.
Signed-off-by: NLubomir Rintel <lkundrak@v3.sk>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
Cc: linux-rpi-kernel@lists.infradead.org
Cc: linux-watchdog@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org

This change updates the ti-soc-thermal driver to use
standard GPIO DT bindings to read the GPIO number associated
to thermal shutdown IRQ, in case the device features it.

Previously, the code was using a specific DT bindings.
As now OMAP supports the standard way to model GPIOs,
there is no point in having a ti specific binding.

Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: linux-pm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: NEduardo Valentin <eduardo.valentin@ti.com>

Add devicetree support for imx framebuffer driver. It uses the generic
display bindings and helper functions.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>

Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc
controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to
always be set.

There also seem to be no other modifications (additional register etc)
present, so to keep the footprint low, add this small variant to the
pltfm driver.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSeungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

This patch adds Device Tree support to the shdma driver. No special DT
properties are used, only standard DMA DT bindings are implemented. Since
shdma controllers reside on SoCs, their configuration is SoC-specific and
shall be passed to the driver from the SoC platform data, using the
auxdata procedure.
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

For most devices the FIFO configuration is the same i.e. when half FIFO size is
available/filled, a source/destination request is serviced. But USART devices
have to do it when there is enough space/data available to perform a single
AHB access so the ASAP configuration.
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Update imx-sdma driver to adopt generic DMA device tree bindings.  It
calls of_dma_controller_register() with imx-sdma specific of_dma_xlate
to get the generic DMA device tree helper support.  The #dma-cells for
imx-sdma must be 3, which includes request ID, peripheral type and
priority.

The existing way of requesting channel, clients directly call
dma_request_channel(), still work there, and will be removed after
all imx-sdma clients get converted to generic DMA device tree helper.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Adding devicetree support for imx-dma driver. Use driver name for
function 'imx_dma_is_general_purpose' because the devicename for
devicetree initialized devices is different.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Reviewed-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

This patch adds phy reset callback support for stmmac driver via device
trees. It adds three new properties to gmac device tree bindings to
define the reset signal via gpio.

With this patch users can conveniently pass reset gpio number with pre,
pulse and post delay in micro secs via DTs.

 active low:
		_________		 ____________
	<pre-delay>	|<pulse-delay>	|<post-delay>
		 	|		|
		 	|_______________|

 active high:
 			 ________________
	<pre-delay>	|<pulse-delay>	|<post-delay>
			|		|
		________|		|___________
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch adds dt support to dwmac version 3.610 and 3.710 these
versions are integrated in STiH415 and STiH416 ARM A9 SOCs.
To support these IP version, some of the device tree properties are
extended.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Changed volatage to voltage.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NMark Brown <broonie@linaro.org>

Changed volatage to voltage.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NMark Brown <broonie@linaro.org>

Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

Instead of allocating a struct pps_gpio_platform_data in the DT case,
store the necessary information in struct pps_gpio_device_data itself.
This avoids an additional allocation and the ifdef.  It also gets rid of
some indirection.

Also use dev_err instead of pr_err in the changed code.
Signed-off-by: NJan Luebbe <jlu@pengutronix.de>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NRodolfo Giometti <giometti@enneenne.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

This is a simple driver for the global timer module found in the Cortex
A9-MP cores from revision r1p0 onwards. This should be able to perform
the functions of the system timer and the local timer in an SMP system.

The global timer has the following features:
    The global timer is a 64-bit incrementing counter with an
auto-incrementing feature. It continues incrementing after sending
interrupts. The global timer is memory mapped in the private memory
region.
    The global timer is accessible to all Cortex-A9 processors in the
cluster. Each Cortex-A9 processor has a private 64-bit comparator that
is used to assert a private interrupt when the global timer has reached
the comparator value. All the Cortex-A9 processors in a design use the
banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
Controller as a Private Peripheral Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Rob Herring <robherring2@gmail.com>
CC: Linus Walleij <linus.walleij@linaro.org>
CC: Will Deacon <will.deacon@arm.com>
CC: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

s5m8767 regulator is used on Exynos platforms which use pin controller
to configure GPIOs. Update the example accordingly.

[This had previously been broken by code changes which failed to update
the documentation -- broonie]
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NMark Brown <broonie@linaro.org>

Signed-off-by: NDaniel Mack <zonque@gmail.com>
Signed-off-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>

This patch add a DT enabled driver for timers found on Marvell Orion SoCs
(Kirkwood, Dove, Orion5x, and Discovery Innovation). It installs a free-
running clocksource on timer0 and a clockevent source on timer1.
Corresponding device tree documentation is also added.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Tested-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: NAndrew Lunn <andrew@lunn.ch>

The OLPC XO-1.75 and XO-4 laptops include a PS/2 touchpad and an AT
keyboard, yet they do not have a hardware PS/2 controller. Instead, a
firmware runs on a dedicated core ("Security Processor", part of the SoC)
that acts as a PS/2 controller through bit-banging.

Communication between the main cpu (Application Processor) and the
Security Processor happens via a standard command mechanism implemented
by the SoC. Add a driver for this interface to enable keyboard/mouse
input on this platform.

Original author: Saadia Baloch
Signed-off-by: NDaniel Drake <dsd@laptop.org>
Signed-off-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>

This patch adds Device Tree support to max8998 driver.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NMark Brown <broonie@linaro.org>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

Add compatible property for the Exynos5250 and enable the frame start
and frame end interrupts. These interrupts are needed for the Exynos5
FIMC-IS firmware. The driver enables those interrupt only where available,
depending on the 'compatible' property. This can be optimized further,
by exposing some API at the subdev driver, so the host driver can enable
extra interrupts only for the image processing chains involving FIMC-IS.
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com
Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>

This patch adds support for the Exynos5250 SoC variant of the FIMC-LITE
IP. A 'compatible' string is added for Exynos5250 compatible devices
and the capture DMA handling is reworked to use the FLITE_REG_CIFCNTSEQ
register, masking output DMA buffer address slots. The frame interrupt
is enabled so there are now 2 interrupts per frame. This likely can be
optimized in future by using any status registers that allow to figure
out what the last and the currently written frame buffer is. It would
also be more reliable in cases where there are high interrupt service
latencies.
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NArun Kumar K <arun.kk@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com
Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>

Add support for exynos5420 mixer IP in the drm mixer driver.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Acked-by: NSeung-Woo Kim <sw0312.kim@samsung.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

This patch adds new combatible strings for hdmi, mixer, ddc
and hdmiphy. It follows the convention of using compatible string
which represent the SoC in which the IP was added for the first
time.

Drivers continue to support the previous compatible strings
but further addition of these compatible strings in device tree
is deprecated.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

Adding support for max-pixelclock and max-width device tree
entries. As some devices that use the tilcdc hardware module
have restrictions on the allowed/tested values.  Also update DT
bindings document to reflect new parameters.
Signed-off-by: NDarren Etheridge <detheridge@ti.com>
Acked-by: NRob Clark <robdclark@gmail.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

GMT G762/763 fan speed PWM controller is connected directly to a fan
and performs closed-loop or open-loop control of the fan speed. Two
modes - PWM or DC - are supported by the chip. Introduced driver
provides various knobs to control the operations of the chip (via
sysfs interface). Specific characteristics of the system can be passed
either using board init code or via DT. Documentation for both the
driver and DT bindings are also provided.
Signed-off-by: NArnaud Ebalard <arno@natisbad.org>
Tested-by: NSimon Guinot <simon.guinot@sequanux.org>
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>

Adding another way that is device tree to pass the shunt resistor
value to driver except for platform data.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
[Guenter Roeck: Added missing of.h include]
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>