1. 17 7月, 2012 7 次提交
  2. 02 7月, 2012 1 次提交
  3. 07 6月, 2012 1 次提交
  4. 04 6月, 2012 1 次提交
    • J
      iommu/amd: Cache pdev pointer to root-bridge · c1bf94ec
      Joerg Roedel 提交于
      At some point pci_get_bus_and_slot started to enable
      interrupts. Since this function is used in the
      amd_iommu_resume path it will enable interrupts on resume
      which causes a warning. The fix will use a cached pointer
      to the root-bridge to re-enable the IOMMU in case the BIOS
      is broken.
      
      Cc: stable@vger.kernel.org
      Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>
      c1bf94ec
  5. 23 3月, 2012 1 次提交
  6. 15 3月, 2012 2 次提交
  7. 09 3月, 2012 1 次提交
  8. 08 3月, 2012 1 次提交
  9. 01 3月, 2012 1 次提交
    • J
      iommu/amd: Split amd_iommu_init function · 8704a1ba
      Joerg Roedel 提交于
      The hardware-initializtion part of the AMD IOMMU driver is
      split out into a seperate function. This function can now be
      called either from amd_iommu_init() itself or any other
      place if the hardware needs to be ready earlier. This will
      be used to implement interrupt remapping for AMD.
      Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>
      8704a1ba
  10. 22 12月, 2011 2 次提交
  11. 12 12月, 2011 7 次提交
  12. 21 6月, 2011 1 次提交
  13. 06 6月, 2011 1 次提交
  14. 10 5月, 2011 1 次提交
  15. 12 4月, 2011 1 次提交
  16. 11 4月, 2011 1 次提交
  17. 07 4月, 2011 1 次提交
    • J
      x86/amd-iommu: Flush all internal TLBs when IOMMUs are enabled · 7d0c5cc5
      Joerg Roedel 提交于
      The old code only flushed a DTE or a domain TLB before it is
      actually used by the IOMMU driver. While this is efficient
      and works when done right it is more likely to introduce new
      bugs when changing code (which happened in the past).
      This patch adds code to flush all DTEs and all domain TLBs
      in each IOMMU right after it is enabled (at boot and after
      resume). This reduces the complexity of the driver and makes
      it less likely to introduce stale-TLB bugs in the future.
      Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>
      7d0c5cc5
  18. 24 3月, 2011 1 次提交
    • R
      x86: Use syscore_ops instead of sysdev classes and sysdevs · f3c6ea1b
      Rafael J. Wysocki 提交于
      Some subsystems in the x86 tree need to carry out suspend/resume and
      shutdown operations with one CPU on-line and interrupts disabled and
      they define sysdev classes and sysdevs or sysdev drivers for this
      purpose.  This leads to unnecessarily complicated code and excessive
      memory usage, so switch them to using struct syscore_ops objects for
      this purpose instead.
      
      Generally, there are three categories of subsystems that use
      sysdevs for implementing PM operations: (1) subsystems whose
      suspend/resume callbacks ignore their arguments entirely (the
      majority), (2) subsystems whose suspend/resume callbacks use their
      struct sys_device argument, but don't really need to do that,
      because they can be implemented differently in an arguably simpler
      way (io_apic.c), and (3) subsystems whose suspend/resume callbacks
      use their struct sys_device argument, but the value of that argument
      is always the same and could be ignored (microcode_core.c).  In all
      of these cases the subsystems in question may be readily converted to
      using struct syscore_ops objects for power management and shutdown.
      Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl>
      Reviewed-by: NThomas Gleixner <tglx@linutronix.de>
      Acked-by: NIngo Molnar <mingo@elte.hu>
      f3c6ea1b
  19. 13 10月, 2010 2 次提交
  20. 23 9月, 2010 2 次提交
    • J
      x86/amd-iommu: Work around S3 BIOS bug · 4c894f47
      Joerg Roedel 提交于
      This patch adds a workaround for an IOMMU BIOS problem to
      the AMD IOMMU driver. The result of the bug is that the
      IOMMU does not execute commands anymore when the system
      comes out of the S3 state resulting in system failure. The
      bug in the BIOS is that is does not restore certain hardware
      specific registers correctly. This workaround reads out the
      contents of these registers at boot time and restores them
      on resume from S3. The workaround is limited to the specific
      IOMMU chipset where this problem occurs.
      
      Cc: stable@kernel.org
      Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>
      4c894f47
    • J
      x86/amd-iommu: Set iommu configuration flags in enable-loop · e9bf5197
      Joerg Roedel 提交于
      This patch moves the setting of the configuration and
      feature flags out out the acpi table parsing path and moves
      it into the iommu-enable path. This is needed to reliably
      fix resume-from-s3.
      
      Cc: stable@kernel.org
      Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>
      e9bf5197
  21. 27 8月, 2010 2 次提交
    • K
      x86, GART/AMD-VI: Make AMD GART and IOMMU use IOMMU_INIT_* macros. · 22e6daf4
      Konrad Rzeszutek Wilk 提交于
      We utilize the IOMMU_INIT macros to create this dependency:
      
                     [null]
                       |
             [pci_xen_swiotlb_detect]
                       |
             [pci_swiotlb_detect_override]
                       |
             [pci_swiotlb_detect_4gb]
                       |
               +-------+--------+
              /                  \
      [detect_calgary]    [gart_iommu_hole_init]
                                  |
                          [amd_iommu_detect]
      
      Meaning that 'amd_iommu_detect' will be called after
      'gart_iommu_hole_init'.
      Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      LKML-Reference: <1282845485-8991-9-git-send-email-konrad.wilk@oracle.com>
      CC: Fujita Tomonori <fujita.tomonori@lab.ntt.co.jp>
      CC: Joerg Roedel <joerg.roedel@amd.com>
      CC: Thomas Gleixner <tglx@linutronix.de>
      CC: Ingo Molnar <mingo@redhat.com>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      22e6daf4
    • K
      x86, iommu: Make all IOMMU's detection routines return a value. · 480125ba
      Konrad Rzeszutek Wilk 提交于
      We return 1 if the IOMMU has been detected. Zero or an error number
      if we failed to find it. This is in preperation of using the IOMMU_INIT
      so that we can detect whether an IOMMU is present. I have not
      tested this for regression on Calgary, nor on AMD Vi chipsets as
      I don't have that hardware.
      
      CC: Muli Ben-Yehuda <muli@il.ibm.com>
      CC: "Jon D. Mason" <jdmason@kudzu.us>
      CC: "Darrick J. Wong" <djwong@us.ibm.com>
      CC: Jesse Barnes <jbarnes@virtuousgeek.org>
      CC: David Woodhouse <David.Woodhouse@intel.com>
      CC: Chris Wright <chrisw@sous-sol.org>
      CC: Yinghai Lu <yinghai@kernel.org>
      CC: Joerg Roedel <joerg.roedel@amd.com>
      CC: H. Peter Anvin <hpa@zytor.com>
      CC: Fujita Tomonori <fujita.tomonori@lab.ntt.co.jp>
      Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      LKML-Reference: <1282845485-8991-3-git-send-email-konrad.wilk@oracle.com>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      480125ba
  22. 01 6月, 2010 2 次提交